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m68hc08 microcontrollers freescale.com mc68hc908sr12 mc68hc08sr12 data sheet mc68hc908sr12 rev. 5.0 07/2004

mc68hc908sr12?mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor 3 mc68hc908sr12 mc68hc08sr12 data sheet to provide the most up-to-date info rmation, the re vision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to veri fy you have the latest information available, refer to: http://www.freescale.com the following revision history table summarizes cha nges contained in this document. for your conven ience, the page number designators have been linked to the appropriate location. freescale and the freescale logo are trademarks of freescale semiconductor, inc. this product incorporates superflash? technology lic ensed from sst. ? freescale semiconductor, inc., 2004
revision history data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 4 freescale semiconductor revision history date revision level description page number(s) july 2004 5 table 24-2 . operating range and table 24-11 . 3v adc electrical characteristics ? changed minimum v dd for adc operation to 3v. 373, 381 15.8.4 adc auto-scan mode data registers (adrl1?adrl3) ? corrected adrl?adrl3 register bits. 248 february, 2002 4 ptb0/sda0, ptb1/scl0, ptb2/sda1/txd, and ptb3/scl1/rxd pins ? clarified these open-drain pins throughout this document. 323, 254, 293 8.4.6 programming the pll ? deleted redundant step in programming the pll. 120 figure 10-1 . monitor mode circuit ? corrected connections for pta1 and pta2. 167 table 10-1 . monitor mode signal requirements and options ? clarified clock input requirements for monitor mode entry. 169 section 11. timer interface module (tim) ? timer discrepancies corrected throughout this section. 181 18.5.1 port c data register (ptc) and 18.5.2 data direction register c (ddrc) ? added notes for ptc6 and ptc7 on 42-pin package. 327, 329 figure 19-3 . irq2 block diagram and 19.5 irq1 and irq2 pins ? corrected irq2 for bih and bil instructions. 338, 339 table 24-4 . 5v dc electrical characteristics and table 24-5 . 3v dc electrical characteristics ? added additional i dd measurements. 374, 376 table 24-13 . current detection electrical characteristics ? updated trip point values. 382 appendix a. mc68hc08sr12 ? added appendix for rom part: mc68hc08sr12. 393
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor list of sections 5 data sheet ? mc68hc9 08sr12mc68hc08sr12 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 35 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 45 section 3. random-a ccess memory (ram) . . . . . . . . . . 61 section 4. flash memory . . . . . . . . . . . . . . . . . . . . . . . . 63 section 5. configuration and mask option registers (config & mor) . . . . . . . . . . . . . . . . . . . . . . 73 section 6. central processor unit (cpu) . . . . . . . . . . . . 81 section 7. oscillator (osc ) . . . . . . . . . . . . . . . . . . . . . . 101 section 8. clock generator modu le (cgm) . . . . . . . . . . 111 section 9. system integration module (sim) . . . . . . . . 141 section 10. monitor rom (mon) . . . . . . . . . . . . . . . . . . 165 section 11. timer interface module (tim) . . . . . . . . . . . 181 section 12. timebase module (tbm ). . . . . . . . . . . . . . . 205 section 13. pulse width modulato r (pwm) . . . . . . . . . . 211 section 14. analog module . . . . . . . . . . . . . . . . . . . . . . 221 section 15. analog-to-digital converter (adc) . . . . . . 231 section 16. serial communicat ions interface (sci) . . . 251 section 17. multi-master iic in terface (mmiic) . . . . . . . 291 section 18. input/output (i/o) port s . . . . . . . . . . . . . . . 317 section 19. external interrupt (irq ) . . . . . . . . . . . . . . . 335
list of sections data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 6 list of sections freescale semiconductor section 20. keyboard interrupt module (kbi). . . . . . . . 343 section 21. computer operatin g properly (cop) . . . . 351 section 22. low-voltage inhibit (lvi) . . . . . . . . . . . . . . 357 section 23. break module (brk) . . . . . . . . . . . . . . . . . . 363 section 24. electrical sp ecifications. . . . . . . . . . . . . . . 371 section 25. mechanical specificati ons . . . . . . . . . . . . . 387 section 26. ordering in formation . . . . . . . . . . . . . . . . . 391 appendix a. mc68hc08sr 12 . . . . . . . . . . . . . . . . . . . . 393
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor table of contents 7 data sheet ? mc68hc9 08sr12mc68hc08sr12 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 1.6.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . . 42 1.6.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 42 1.6.3 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.6.4 external interrupt pin (irq1 ) . . . . . . . . . . . . . . . . . . . . . . . .43 1.6.5 analog power supply pin (v dda ) . . . . . . . . . . . . . . . . . . . . .43 1.6.6 analog ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.6.7 adc voltage low reference pin (v refl ) . . . . . . . . . . . . . . 43 1.6.8 adc voltage hi gh reference pin (v refh ). . . . . . . . . . . . . . 43 1.6.9 external filter capac itor pin (cgmxfc) . . . . . . . . . . . . . . . 43 1.6.10 analog input pins (o pin1/atd0, opin2/atd1, v ssam ). . .44 1.6.11 port a input/output (i/o) pins (pta7?pta0) . . . . . . . . . . . . 44 1.6.12 port b i/o pins (ptb6?p tb0) . . . . . . . . . . . . . . . . . . . . . . . 44 1.6.13 port c i/o pins (ptc7?p tc0) . . . . . . . . . . . . . . . . . . . . . . . 44 1.6.14 port d i/o pins (ptd7/kbi7?ptd0/ kbi0) . . . . . . . . . . . . . . 44 section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.3 unimplemented memory loc ations . . . . . . . . . . . . . . . . . . . . . 45
table of contents data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 8 table of contents freescale semiconductor 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 section 4. flash memory 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.5 flash page erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .68 4.8 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.8.1 flash block protect regi ster . . . . . . . . . . . . . . . . . . . . . . . 70 section 5. configuration and mask option registers (config & mor) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 5.4 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . . 75 5.5 configuration register 2 (config2) . . . . . . . . . . . . . . . . . . . . 77 5.6 mask option register (mor) . . . . . . . . . . . . . . . . . . . . . . . . . . 79
table of contents mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor table of contents 9 section 6. central pr ocessor unit (cpu) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 6.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 section 7. oscillator (osc) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.3 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.3.1 cgm reference clock selection . . . . . . . . . . . . . . . . . . . . 104 7.3.2 tbm reference clock selection . . . . . . . . . . . . . . . . . . . . 105 7.4 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.5 rc oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.6 x-tal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.7.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . 108 7.7.2 crystal amplifier ou tput pin (osc2) . . . . . . . . . . . . . . . . . 109
table of contents data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 10 table of contents freescale semiconductor 7.7.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . 109 7.7.4 cgm oscillator clock (cgmxclk) . . . . . . . . . . . . . . . . . . 109 7.7.5 cgm reference clock (cgmrclk) . . . . . . . . . . . . . . . . . 109 7.7.6 oscillator clock to time base module (oscclk) . . . . . . . 109 7.8 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 7.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 7.9 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . 110 section 8. clock generator module (cgm) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 8.4.1 oscillator module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.4.2 phase-locked loop circ uit (pll) . . . . . . . . . . . . . . . . . . . 116 8.4.3 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.4.4 acquisition and tracking modes . . . . . . . . . . . . . . . . . . . . 118 8.4.5 manual and automati c pll bandwidth modes. . . . . . . . . . 118 8.4.6 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.4.7 special programming exceptions . . . . . . . . . . . . . . . . . . . 124 8.4.8 base clock selector ci rcuit . . . . . . . . . . . . . . . . . . . . . . . . 124 8.4.9 cgm external connectio ns . . . . . . . . . . . . . . . . . . . . . . . . 125 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.5.1 external filter capacitor pin (c gmxfc) . . . . . . . . . . . . . . 126 8.5.2 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . 126 8.5.3 pll anal og ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . 126 8.5.4 oscillator output frequency signal (cgmxc lk) . . . . . . . 126 8.5.5 cgm reference clock (cgmrclk) . . . . . . . . . . . . . . . . . 126 8.5.6 cgm vco clock output (cgmvclk) . . . . . . . . . . . . . . . . 127 8.5.7 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . . 127 8.5.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . 127 8.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.6.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
table of contents mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor table of contents 11 8.6.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . .130 8.6.3 pll multiplier select registers . . . . . . . . . . . . . . . . . . . . . 132 8.6.4 pll vco range select register . . . . . . . . . . . . . . . . . . . .133 8.6.5 pll reference divider select register . . . . . . . . . . . . . . . 134 8.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 8.8 special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 8.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 8.8.3 cgm during break inte rrupts. . . . . . . . . . . . . . . . . . . . . . . 136 8.9 acquisition/lock time spec ifications . . . . . . . . . . . . . . . . . . . 137 8.9.1 acquisition/lock time definitions. . . . . . . . . . . . . . . . . . . .137 8.9.2 parametric influences on reaction time . . . . . . . . . . . . . . 137 8.9.3 choosing a filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 section 9. system integration module (sim) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 144 9.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9.3.2 clock start-up from po r or lvi reset. . . . . . . . . . . . . . . . 145 9.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . 146 9.4 reset and system initiali zation. . . . . . . . . . . . . . . . . . . . . . . . 146 9.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 9.4.2 active resets from in ternal sources . . . . . . . . . . . . . . . . . 147 9.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 9.4.2.2 computer operati ng properly (cop) rese t. . . . . . . . . . 149 9.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . .150 9.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 150 9.4.2.6 monitor mode entry module rese t. . . . . . . . . . . . . . . . . 150 9.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . 151 9.5.2 sim counter during stop mode re covery . . . . . . . . . . . . . 151 9.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 151
table of contents data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 12 table of contents freescale semiconductor 9.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 9.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 9.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 9.6.1.3 interrupt status r egisters . . . . . . . . . . . . . . . . . . . . . . .155 9.6.1.4 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . 155 9.6.1.5 interrupt stat us register 2 . . . . . . . . . . . . . . . . . . . . . . . 157 9.6.1.6 interrupt stat us register 3 . . . . . . . . . . . . . . . . . . . . . . . 157 9.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 9.6.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 9.6.4 status flag protection in break mode . . . . . . . . . . . . . . . . 158 9.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 9.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 9.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 9.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 9.8.1 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 162 9.8.2 sim reset status regist er . . . . . . . . . . . . . . . . . . . . . . . . 163 9.8.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . 164 section 10. monitor rom (mon) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 10.4.3 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 10.4.4 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 10.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
table of contents mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor table of contents 13 section 11. timer interface module (tim) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 11.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 188 11.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .189 11.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 189 11.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 190 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 191 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 11.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.10.1 tim status and control register . . . . . . . . . . . . . . . . . . . . 196 11.10.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 11.10.3 tim counter modulo r egisters . . . . . . . . . . . . . . . . . . . . . 199 11.10.4 tim channel status and control registers . . . . . . . . . . . . 200 11.10.5 tim channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 section 12. timebase module (tbm) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
table of contents data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 14 table of contents freescale semiconductor 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 12.5 timebase register description. . . . . . . . . . . . . . . . . . . . . . . . 207 12.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 12.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 12.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 section 13. pulse width modulator (pwm) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 13.4 pwm period and resolution. . . . . . . . . . . . . . . . . . . . . . . . . . 214 13.5 pwm automatic phase cont rol . . . . . . . . . . . . . . . . . . . . . . .215 13.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 13.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 13.8 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 13.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 13.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 13.10.1 pwm control register (pwmcr) . . . . . . . . . . . . . . . . . . . 217 13.10.2 pwm clock control register (pwmccr) . . . . . . . . . . . . . 218 13.10.3 pwm data registers (pwmdr0 ?pwmdr2) . . . . . . . . . . 219 13.10.4 pwm phase control register . . . . . . . . . . . . . . . . . . . . . . 220 section 14. analog module 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
table of contents mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor table of contents 15 14.4.1 on-chip temperature sensor . . . . . . . . . . . . . . . . . . . . . . 223 14.4.2 two-stage amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 14.4.3 amplifier response time . . . . . . . . . . . . . . . . . . . . . . . . . . 224 14.4.4 current flow detecti on amplifier . . . . . . . . . . . . . . . . . . . . 225 14.4.5 current flow detect ou tput . . . . . . . . . . . . . . . . . . . . . . . . 225 14.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 14.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 14.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 14.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 14.7 analog module i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . 226 14.7.1 analog module control register (amcr) . . . . . . . . . . . . . 226 14.7.2 analog module gain control r egister (amgcr) . . . . . . . . 227 14.7.3 analog module status and co ntrol register (amscr) . . . 228 section 15. analog-to-dig ital converter (adc) 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 15.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 15.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 15.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 15.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.4.5 auto-scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.4.6 result justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 15.4.7 data register interlocki ng . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.4.8 monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 15.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 15.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 15.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.7.1 adc voltage in (v adin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
table of contents data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 16 table of contents freescale semiconductor 15.7.2 adc analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . 240 15.7.3 adc analog ground pin (v ssa ). . . . . . . . . . . . . . . . . . . . . 240 15.7.4 adc voltage reference high pin (v refh ). . . . . . . . . . . . . 241 15.7.5 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . 241 15.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 15.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . .242 15.8.2 adc clock control regi ster. . . . . . . . . . . . . . . . . . . . . . . . 244 15.8.3 adc data register 0 (adrh0 and a drl0). . . . . . . . . . . . 246 15.8.4 adc auto-scan mode data registers (adrl1?adrl3). . 248 15.8.5 adc auto-scan control register (adascr). . . . . . . . . . . 248 section 16. serial commun ications interface (sci) 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 16.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 16.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 16.5.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 16.5.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 16.5.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 16.5.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 259 16.5.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 16.5.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 16.5.2.5 inversion of transm itted output. . . . . . . . . . . . . . . . . . . 261 16.5.2.6 transmitter in terrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .261 16.5.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 16.5.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 16.5.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 16.5.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 16.5.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 16.5.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .266 16.5.3.6 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 16.5.3.7 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 16.5.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
table of contents mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor table of contents 17 16.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 16.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 16.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 16.7 sci during break module interrupts. . . . . . . . . . . . . . . . . . . .272 16.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 16.8.1 txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 16.8.2 rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 16.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 16.9.1 sci control regi ster 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 16.9.2 sci control regi ster 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 16.9.3 sci control regi ster 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 16.9.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 16.9.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 16.9.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 16.9.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . .288 section 17. multi-master iic interface (mmiic) 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.5 multi-master iic system configuratio n . . . . . . . . . . . . . . . . . . 295 17.6 multi-master iic bus prot ocol . . . . . . . . . . . . . . . . . . . . . . . . . 295 17.6.1 start signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 17.6.2 slave address transmission . . . . . . . . . . . . . . . . . . . . . . .296 17.6.3 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 17.6.4 repeated start signal . . . . . . . . . . . . . . . . . . . . . . . . . . 297 17.6.5 stop signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 17.6.6 arbitration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 17.6.7 clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 17.6.8 handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 17.6.9 packet error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.7 mmiic i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
table of contents data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 18 table of contents freescale semiconductor 17.7.1 mmiic address register (mmadr) . . . . . . . . . . . . . . . . . . 299 17.7.2 mmiic control register 1 (mmcr1) . . . . . . . . . . . . . . . . . 301 17.7.3 mmiic control register 2 (mmcr2) . . . . . . . . . . . . . . . . . 303 17.7.4 mmiic status register (mmsr). . . . . . . . . . . . . . . . . . . . . 305 17.7.5 mmiic data transmit register (mmdtr) . . . . . . . . . . . . . 307 17.7.6 mmiic data receive register (m mdrr). . . . . . . . . . . . . . 308 17.7.7 mmiic crc data register (mm crcdr). . . . . . . . . . . . . . 309 17.7.8 mmiic frequency divider register (mmfdr) . . . . . . . . . . 310 17.8 program algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 17.8.1 data sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 17.9 smbus protocols with pec and with out pec. . . . . . . . . . . . . 313 17.9.1 quick command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 17.9.2 send byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 17.9.3 receive byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 17.9.4 write byte/word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 17.9.5 read byte/word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 17.9.6 process call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 17.9.7 block read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 17.10 smbus protocol implementation . . . . . . . . . . . . . . . . . . . . . . 316 section 18. input/output (i/o) ports 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 18.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 18.3.1 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . 320 18.3.2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 321 18.3.3 port a led control register (leda ) . . . . . . . . . . . . . . . . . 323 18.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 18.4.1 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . 324 18.4.2 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 325 18.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 18.5.1 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . 327 18.5.2 data direction register c (ddrc). . . . . . . . . . . . . . . . . . . 329 18.5.3 port c led control register (ledc ) . . . . . . . . . . . . . . . . . 330
table of contents mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor table of contents 19 18.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 18.6.1 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . 331 18.6.2 data direction register d (ddrd). . . . . . . . . . . . . . . . . . . 332 section 19. external interrupt (irq) 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 19.5 irq1 and irq2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 19.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 339 19.7 irq registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 19.7.1 irq1 status an d control register . . . . . . . . . . . . . . . . . . . 340 19.7.2 irq2 status an d control register . . . . . . . . . . . . . . . . . . . 341 section 20. keyboard in terrupt module (kbi) 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 20.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 20.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 20.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345 20.5.1 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 20.6 keyboard interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . 347 20.6.1 keyboard status and control register. . . . . . . . . . . . . . . . 348 20.6.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 349 20.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 20.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349 20.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349 20.10 keyboard module during break inte rrupts . . . . . . . . . . . . . . . 350
table of contents data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 20 table of contents freescale semiconductor section 21. computer op erating properly (cop) 21.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 21.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352 21.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 21.4.1 iclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 21.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 21.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 21.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 21.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 21.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 21.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 21.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 354 21.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 21.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 21.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 21.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 21.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356 21.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356 21.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 356 section 22. low-volt age inhibit (lvi) 22.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 22.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 22.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 22.4.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 22.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . .360 22.4.3 voltage hysteresis protection . . . . . . . . . . . . . . . . . . . . . . 360 22.4.4 lvi trip selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 22.5 lvi status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
table of contents mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor table of contents 21 22.6 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361 22.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 22.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 22.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 section 23. break module (brk) 23.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 23.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 23.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364 23.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 366 23.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .366 23.4.3 tim1 and tim2 during break interr upts. . . . . . . . . . . . . . . 366 23.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 366 23.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 23.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366 23.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367 23.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 23.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 367 23.6.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 368 23.6.3 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 368 23.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . 370 section 24. electrical specifications 24.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 24.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 372 24.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 373 24.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 24.6 5.0v dc electrical charac teristics . . . . . . . . . . . . . . . . . . . . . 374 24.7 3.0v dc electrical charac teristics . . . . . . . . . . . . . . . . . . . . . 376
table of contents data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 22 table of contents freescale semiconductor 24.8 5.0v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 24.9 3.0v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 24.10 5.0v oscillator characte ristics . . . . . . . . . . . . . . . . . . . . . . . . 378 24.11 3.0v oscillator characte ristics . . . . . . . . . . . . . . . . . . . . . . . . 379 24.12 5.0v adc electrical c haracteristics . . . . . . . . . . . . . . . . . . . .380 24.13 3.0v adc electrical c haracteristics . . . . . . . . . . . . . . . . . . . .381 24.14 analog module electrical characterist ics . . . . . . . . . . . . . . . . 382 24.14.1 temperature sensor electrical characteristic s . . . . . . . . . 382 24.14.2 current detection el ectrical characteristics. . . . . . . . . . . . 382 24.14.3 two-stage amplifier el ectrical characteristic s. . . . . . . . . . 382 24.15 timer interface module characteristics . . . . . . . . . . . . . . . . . 383 24.16 mmiic electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . 383 24.17 cgm electrical s pecifications. . . . . . . . . . . . . . . . . . . . . . . . . 385 24.18 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 386 section 25. mechanic al specifications 25.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 25.3 48-pin plastic low quad flat pack (lqfp) . . . . . . . . . . . . . . 388 25.4 42-pin shrink dual in -line package (sdip) . . . . . . . . . . . . . . 389 section 26. ordering information 26.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391 26.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 26.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
table of contents mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor table of contents 23 appendix a. mc68hc08sr12 a.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393 a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 a.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 a.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 a.5 mask option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 a.6 reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 a.7 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397 a.8 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 a.8.1 5.0v dc electric al characteristics . . . . . . . . . . . . . . . . . . . 398 a.8.2 3.0v dc electric al characteristics . . . . . . . . . . . . . . . . . . . 399 a.8.3 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 a.9 rom order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
table of contents data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 24 table of contents freescale semiconductor
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor list of figures 25 data sheet ? mc68hc9 08sr12mc68hc08sr12 list of figures figure title page 1-1 mc68hc908sr12 block diagram . . . . . . . . . . . . . . . . . . . . . . 39 1-2 48-pin lqfp pin a ssignments . . . . . . . . . . . . . . . . . . . . . . . . . 40 1-3 42-pin sdip pin a ssignment . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1-4 power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2-2 control, status, and data registers . . . . . . . . . . . . . . . . . . . . .48 4-1 flash i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . 64 4-2 flash control regist er (flcr) . . . . . . . . . . . . . . . . . . . . . . . 65 4-3 flash programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . 69 4-4 flash block protect register (flbpr). . . . . . . . . . . . . . . . . . 70 4-5 flash block protec t start address . . . . . . . . . . . . . . . . . . . . .70 5-1 config and mor register summary. . . . . . . . . . . . . . . . . . . 74 5-2 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . . 75 5-3 configuration register 2 (config2) . . . . . . . . . . . . . . . . . . . . 77 5-4 mask option register (mor) . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6-3 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 6-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 86 7-1 oscillator module block di agram . . . . . . . . . . . . . . . . . . . . . . 103 7-2 mask option register (mor) . . . . . . . . . . . . . . . . . . . . . . . . . 104 7-3 configuration register 2 (config2) . . . . . . . . . . . . . . . . . . . 105 7-4 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
list of figures data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 26 list of figures freescale semiconductor figure title page 7-5 rc oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7-6 crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8-1 cgm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8-2 cgm i/o register summar y. . . . . . . . . . . . . . . . . . . . . . . . . . 115 8-3 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8-4 pll control register (pc tl) . . . . . . . . . . . . . . . . . . . . . . . . . 128 8-5 pll bandwidth control register (pbwcr) . . . . . . . . . . . . . . 131 8-6 pll multiplier select register high (pmsh) . . . . . . . . . . . . . 132 8-7 pll multiplier select register low (pmsl) . . . . . . . . . . . . . . 132 8-8 pll vco range se lect register (pmrs) . . . . . . . . . . . . . . . 133 8-9 pll reference div ider select register (pm ds) . . . . . . . . . . 134 8-10 pll filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9-1 sim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9-2 sim i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .144 9-3 cgm clock signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9-4 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 9-5 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9-6 sources of internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9-7 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9-8 interrupt entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9-9 interrupt recovery timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9-10 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 9-11 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . . 154 9-12 interrupt status register 1 (int1). . . . . . . . . . . . . . . . . . . . . . 155 9-13 interrupt status register 2 (int2). . . . . . . . . . . . . . . . . . . . . . 157 9-14 interrupt status register 3 (int3). . . . . . . . . . . . . . . . . . . . . . 157 9-15 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 9-16 wait recovery from interrupt or br eak . . . . . . . . . . . . . . . . . . 160 9-17 wait recovery from internal reset. . . . . . . . . . . . . . . . . . . . . 160 9-18 stop mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 9-19 stop mode recovery fr om interrupt or break . . . . . . . . . . . . . 161 9-20 sim break status regist er (sbsr) . . . . . . . . . . . . . . . . . . . . 162 9-21 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . . . 163 9-22 sim break flag control register (s bfcr) . . . . . . . . . . . . . . 164
list of figures mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor list of figures 27 figure title page 10-1 monitor mode circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 10-2 low-voltage monitor m ode entry flowchart. . . . . . . . . . . . . . 171 10-3 monitor data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 10-4 break transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 10-5 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 10-6 write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 10-7 stack pointer at monitor mode entry . . . . . . . . . . . . . . . . . . . 178 10-8 monitor mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . .179 11-1 tim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 11-2 tim i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .185 11-3 pwm period and pulse wi dth . . . . . . . . . . . . . . . . . . . . . . . . 190 11-4 tim status and control register (tsc ) . . . . . . . . . . . . . . . . . 196 11-5 tim counter registers high (tcnth) . . . . . . . . . . . . . . . . . . 198 11-6 tim counter registers low (tcntl) . . . . . . . . . . . . . . . . . . . 198 11-7 tim counter modulo r egister high (tmodh) . . . . . . . . . . . . 199 11-8 tim counter modulo r egister low (tmodl) . . . . . . . . . . . . . 199 11-9 tim channel 0 status and control register (tsc0) . . . . . . . 200 11-10 tim channel 1 status and control register (t sc1) . . . . . . . 200 11-11 chxmax latenc y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 11-12 tim channel 0 register high (tch0h) . . . . . . . . . . . . . . . . . 204 11-13 tim channel 0 register low (tch0l) . . . . . . . . . . . . . . . . . . 204 11-14 tim channel 1 register high (tch1h) . . . . . . . . . . . . . . . . . 204 11-15 tim channel 1 register low (tch1l) . . . . . . . . . . . . . . . . . . 204 12-1 timebase block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12-2 timebase control register (tbcr) . . . . . . . . . . . . . . . . . . . . 207 13-1 pwm i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . 212 13-2 pwm block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 13-3 pwm output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 13-4 pwm automatic phase cont rol . . . . . . . . . . . . . . . . . . . . . . .215 13-5 pwm control register (pwmcr). . . . . . . . . . . . . . . . . . . . . . 217 13-6 pwm clock control regi ster (pwmccr) . . . . . . . . . . . . . . . 218 13-7 pwm data register 0 (p wmdr0) . . . . . . . . . . . . . . . . . . . . . 219 13-8 pwm data register 1 (p wmdr1) . . . . . . . . . . . . . . . . . . . . . 219
list of figures data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 28 list of figures freescale semiconductor figure title page 13-9 pwm data register 2 (p wmdr2) . . . . . . . . . . . . . . . . . . . . . 219 13-10 pwm phase control register (pwm pcr) . . . . . . . . . . . . . . . 220 14-1 analog module block diagr am . . . . . . . . . . . . . . . . . . . . . . . . 222 14-2 analog module i/o register summary . . . . . . . . . . . . . . . . . . 223 14-3 analog module control register (a mcr). . . . . . . . . . . . . . . . 226 14-4 analog module gain control regi ster (amgcr) . . . . . . . . . . 227 14-5 analog module status and control register (amscr) . . . . . 229 15-1 adc i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . 233 15-2 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 15-3 adc status and control register (adscr) . . . . . . . . . . . . . . 242 15-4 adc clock control regi ster (adiclk). . . . . . . . . . . . . . . . . . 244 15-5 adrh0 and adrl0 in 8-bit truncat ed mode. . . . . . . . . . . . . 246 15-6 adrh0 and adrl0 in right justifi ed mode. . . . . . . . . . . . . . 246 15-7 adrh0 and adrl0 in left justified mode . . . . . . . . . . . . . . . 247 15-8 adrh0 and adrl0 in left justifi ed sign data mode . . . . . . 247 15-9 adc data register low 1 to 3 (adrl 1?adrl3) . . . . . . . . . . 248 15-10 adc scan control regist er (adascr) . . . . . . . . . . . . . . . . . 248 16-1 sci module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .255 16-2 sci i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .256 16-3 sci data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 16-4 sci transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 16-5 sci receiver block diagr am . . . . . . . . . . . . . . . . . . . . . . . . . 263 16-6 receiver data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 16-7 slow data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 16-8 fast data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 16-9 sci control regist er 1 (scc1). . . . . . . . . . . . . . . . . . . . . . . . 274 16-10 sci control regist er 2 (scc2). . . . . . . . . . . . . . . . . . . . . . . . 277 16-11 sci control regist er 3 (scc3). . . . . . . . . . . . . . . . . . . . . . . . 279 16-12 sci status register 1 (s cs1) . . . . . . . . . . . . . . . . . . . . . . . . 282 16-13 flag clearing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 16-14 sci status register 2 (s cs2) . . . . . . . . . . . . . . . . . . . . . . . . 286 16-15 sci data register (scdr) . . . . . . . . . . . . . . . . . . . . . . . . . . .287 16-16 sci baud rate register (scbr) . . . . . . . . . . . . . . . . . . . . . . 288
list of figures mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor list of figures 29 figure title page 17-1 mmiic i/o register summa ry. . . . . . . . . . . . . . . . . . . . . . . . . 294 17-2 multi-master iic bus transmissi on signal diagram . . . . . . . . 295 17-3 clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 17-4 mmiic address register (mmadr) . . . . . . . . . . . . . . . . . . . . 299 17-5 mmiic control register 1 (mmcr1). . . . . . . . . . . . . . . . . . . .301 17-6 mmiic control register 2 (mmcr2). . . . . . . . . . . . . . . . . . . .303 17-7 mmiic status register (mmsr) . . . . . . . . . . . . . . . . . . . . . . . 305 17-8 mmiic data transmit register (mmdtr) . . . . . . . . . . . . . . . 307 17-9 mmiic data receive register (mm drr) . . . . . . . . . . . . . . . . 308 17-10 mmiic crc data regi ster (mmcrcdr) . . . . . . . . . . . . . . . . 309 17-11 mmiic frequency divider register (mmfdr) . . . . . . . . . . . . 310 17-12 data transfer sequenc es for master/slave transmit/receive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 312 17-13 quick command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 17-14 send byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 17-15 receive byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 17-16 write byte/word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 17-17 read byte/word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 17-18 process call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 17-19 block read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 17-20 smbus protocol implementation . . . . . . . . . . . . . . . . . . . . . . 316 18-1 i/o port register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .318 18-2 port a data register (pta ) . . . . . . . . . . . . . . . . . . . . . . . . . . 320 18-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . 321 18-4 port a i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 18-5 port a led control regi ster (leda) . . . . . . . . . . . . . . . . . . . 323 18-6 port b data register (ptb ) . . . . . . . . . . . . . . . . . . . . . . . . . . 324 18-7 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 325 18-8 port b i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 18-9 port c data register (ptc ) . . . . . . . . . . . . . . . . . . . . . . . . . . 327 18-10 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 329 18-11 port c i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 18-12 port a led control regi ster (leda) . . . . . . . . . . . . . . . . . . . 330 18-13 port d data register (ptd ) . . . . . . . . . . . . . . . . . . . . . . . . . . 331 18-14 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . . . . 332 18-15 port d i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
list of figures data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 30 list of figures freescale semiconductor figure title page 19-1 external interrupt i/o register summ ary . . . . . . . . . . . . . . . . 336 19-2 irq1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 19-3 irq2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 19-4 irq1 status and cont rol register (intscr1) . . . . . . . . . . . . 340 19-5 irq2 status and cont rol register (intscr2) . . . . . . . . . . . . 341 20-1 kbi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .344 20-2 keyboard interrupt block diagram . . . . . . . . . . . . . . . . . . . . . 345 20-3 keyboard status and control register (kbscr) . . . . . . . . . . 348 20-4 keyboard interrupt enable register (kbier) . . . . . . . . . . . . . 349 21-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 21-2 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . 354 21-3 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . . 355 22-1 lvi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 22-2 lvi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .358 22-3 lvi status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 23-1 break module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 365 23-2 break module i/o register summary . . . . . . . . . . . . . . . . . . . 365 23-3 break status and control register (brkscr). . . . . . . . . . . . 367 23-4 break address register high (brkh) . . . . . . . . . . . . . . . . . . 368 23-5 break address register low (brkl) . . . . . . . . . . . . . . . . . . . 368 23-6 sim break status regist er (sbsr) . . . . . . . . . . . . . . . . . . . . 369 23-7 sim break flag control register (s bfcr) . . . . . . . . . . . . . . 370 24-1 rc vs. bus frequency (5v @25 c) . . . . . . . . . . . . . . . . . . . .378 24-2 rc vs. bus frequency (3v @25 c) . . . . . . . . . . . . . . . . . . . .379 24-3 mmiic signal timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 25-1 48-pin lqfp (cas e #932-02) . . . . . . . . . . . . . . . . . . . . . . . . . 388 25-2 42-pin sdip (case #858-01) . . . . . . . . . . . . . . . . . . . . . . . . . 389 a-1 mc68hc08sr12 block diagr am . . . . . . . . . . . . . . . . . . . . . 395 a-2 mc68hc08sr12 memory ma p . . . . . . . . . . . . . . . . . . . . . . 396
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor list of tables 31 data sheet ? mc68hc9 08sr12mc68hc08sr12 list of tables table title page 2-1 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 5-1 cgmxclk clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6-1 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6-2 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7-1 cgmxclk clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7-2 timebase module refer ence clock selection . . . . . . . . . . . . 105 8-1 numeric examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8-3 vpr1 and vpr0 programming . . . . . . . . . . . . . . . . . . . . . . .130 8-2 pre1 and pre0 programming . . . . . . . . . . . . . . . . . . . . . . .130 9-1 signal name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9-2 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 9-3 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 10-1 monitor mode signal requirements and options . . . . . . . . . . 169 10-2 mode differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 10-3 monitor baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . 173 10-4 read (read memory) command . . . . . . . . . . . . . . . . . . . . . 175 10-5 write (write memory) command. . . . . . . . . . . . . . . . . . . . . 175 10-7 iwrite (indexed write) command . . . . . . . . . . . . . . . . . . . . 176 10-6 iread (indexed read) co mmand . . . . . . . . . . . . . . . . . . . . . 176 10-8 readsp (read stack po inter) command . . . . . . . . . . . . . . . 177 10-9 run (run user program) command . . . . . . . . . . . . . . . . . . . 177 11-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11-2 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
list of tables data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 32 list of tables freescale semiconductor table title page 11-3 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . . 202 12-1 timebase rate selection for oscc lk = 32.768 kh z . . . . . . 207 13-1 ptc0 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 13-2 pwm counter clock prescaler selectio n . . . . . . . . . . . . . . . . 219 14-1 analog module power control . . . . . . . . . . . . . . . . . . . . . . . . 226 14-2 amplifier channel select control bits . . . . . . . . . . . . . . . . . . . 227 14-3 analog module gain values . . . . . . . . . . . . . . . . . . . . . . . . . . 228 14-4 analog module clock divider select. . . . . . . . . . . . . . . . . . . .229 15-1 mux channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 15-2 adc clock divide ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 15-3 adc mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 15-4 auto-scan mode channel se lect . . . . . . . . . . . . . . . . . . . . . . 248 16-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 16-2 start bit verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 16-3 data bit recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 16-4 stop bit recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 16-5 character format selection . . . . . . . . . . . . . . . . . . . . . . . . . . 276 16-6 sci baud rate prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 16-7 sci baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16-8 sci baud rate selection examples . . . . . . . . . . . . . . . . . . . .290 17-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 17-2 mmiic baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . 310 18-1 port control register bits summary. . . . . . . . . . . . . . . . . . . .319 18-2 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 18-3 ptb2 and ptb3 pin conf igurations . . . . . . . . . . . . . . . . . . . .325 18-4 port b pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 18-5 ptc0 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 18-6 port c pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 18-7 port d pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
list of tables mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor list of tables 33 table title page 20-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 22-1 lviout bit indicati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 24-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 372 24-2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 24-3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 24-4 5v dc electrical characte ristics. . . . . . . . . . . . . . . . . . . . . . . 374 24-5 3v dc electrical characte ristics. . . . . . . . . . . . . . . . . . . . . . . 376 24-6 5v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377 24-7 3v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377 24-8 5v oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 378 24-9 3v oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 379 24-10 5v adc electrical char acteristics . . . . . . . . . . . . . . . . . . . . . 380 24-11 3v adc electrical char acteristics . . . . . . . . . . . . . . . . . . . . . 381 24-12 temperature sensor electrical char acteristics . . . . . . . . . . . 382 24-13 current detection electr ical characteristics . . . . . . . . . . . . . . 382 24-14 two-stage amplifier elec trical characteristics . . . . . . . . . . . . 382 24-15 mmiic dc electrical c haracteristics. . . . . . . . . . . . . . . . . . . .383 24-16 mmiic interface input/o utput signal timi ng. . . . . . . . . . . . . . 384 24-17 flash memory electrical characteri stics . . . . . . . . . . . . . . . 386 26-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 a-1 summary of mc68hc08sr12 and mc68hc908sr12 differences . . . . . . . . . . . . . . . . . . . . . 394 a-2 5v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . 398 a-3 3v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . 399 a-4 mc68hc08sr12 order num bers . . . . . . . . . . . . . . . . . . . . . 401
list of tables data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 34 list of tables freescale semiconductor
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor general description 35 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 1.6.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . . 42 1.6.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 42 1.6.3 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.6.4 external interrupt pin (irq1 ) . . . . . . . . . . . . . . . . . . . . . . . .43 1.6.5 analog power supply pin (v dda ) . . . . . . . . . . . . . . . . . . . . .43 1.6.6 analog ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.6.7 adc voltage low reference pin (v refl ) . . . . . . . . . . . . . . 43 1.6.8 adc voltage hi gh reference pin (v refh ). . . . . . . . . . . . . . 43 1.6.9 external filter capac itor pin (cgmxfc) . . . . . . . . . . . . . . . 43 1.6.10 analog input pins (o pin1/atd0, opin2/atd1, v ssam ). . .44 1.6.11 port a input/output (i/o) pins (pta7?pta0) . . . . . . . . . . . . 44 1.6.12 port b i/o pins (ptb6?p tb0) . . . . . . . . . . . . . . . . . . . . . . . 44 1.6.13 port c i/o pins (ptc7?p tc0) . . . . . . . . . . . . . . . . . . . . . . . 44 1.6.14 port d i/o pins (ptd7/kbi7?ptd0/ kbi0) . . . . . . . . . . . . . . 44
data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 36 general description freescale semiconductor general description 1.2 introduction the mc68hc908sr12 is a me mber of the low-co st, high-performance m68hc08 family of 8-bi t microcontroller units (mcus). the m68hc08 family is based on the customer-spec ified integrated circuit (csic) design strategy. all mcus in t he family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types. 1.3 features features of the mc68hc908s r12 include the following: high-performance m68hc08 architecture fully upward-compatible objec t code with m6805, m146805, and m68hc05 families maximum internal bus frequency: ? 8-mhz at 5v op erating voltage ? 4-mhz at 3v op erating voltage clock input options: ? rc-oscillator ? 32khz crystal-oscillator with 32mhz internal phase-lock-loop 12k-bytes user program fla sh memory with security 1 feature 512 bytes of on-chip ram two 16-bit, 2-channel timer inte rface modules (tim1 and tim2) with selectable input captur e, output compare, and pwm capability on each channel timebase module 3-channel, 8-bit high speed pw m (125khz) with independent counters and automatic phase control serial communications interface module (sci) 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users.
general description features mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor general description 37 system management bus (smb us), version 1.0/1.1 (multi-master iic bus) 14-channel, 10-bit analog-to-di gital converter (adc), with auto-scan mode for 4 channels current sensor with programmable amplifier temperature sensor (?20 c to +70 c) irq1 external interrupt pi n with integrated pullup irq2 external interrupt pin with programmable pullup 8-bit keyboard wakeup po rt with integrated pullup 31 general-purpose input/output (i /o) pins and 2 dedicated pins: ? 31 shared-function i/o pins ? two dedicated a nalog input pins low-power design (fully stat ic with stop and wait modes) master reset pin (with integr ated pullup) and power-on reset system protection features ? optional computer operati ng properly (cop) reset ? low-voltage detection with optional reset ? illegal opcode detection with reset ? illegal address detection with reset 48-pin low quad flat pack (lqfp) and 42-pin shri nk dual-in-line package (sdip) specific features of the mc68hc908sr12 in 42-pin sdip are: ? 29 general-purpose l/os only ? 11-channel adc only features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05)
data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 38 general description freescale semiconductor general description 16-bit index regist er and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications efficient c language support 1.4 mcu block diagram figure 1-1 shows the structure of the mc68hc908sr12.
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor general description 39 general description mcu block diagram figure 1-1. mc68h c908sr12 block diagram clock generator module system integration module timebase 2-channel timer interface module 2 low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 96 bytes user flash ? 12,288 bytes user ram ? 512 bytes monitor rom ? 368 bytes user flash vectors ? 38 bytes external irq module ddrb portb internal bus osc1 osc2 cgmxfc * rst * irq1 module interrupt module computer operating properly module v refh ptb6/irq2 ptb5/t2ch1 ptb4/t2ch0 ptb3//scl1/rxd ? ptb2/sda1/txd ? ptb1/scl0 ? ptb0/sda0 ? v refl 2-channel timer interface module 1 phase-locked loop serial communications interface module power-on reset module power v ss v dd v ssa v dda * pin contains int egrated pullup device. ** pin contains conf igurable pullup device. *** pin contains integrated pul lup device for kbi functions. ? pin is open-drain when configured as output. ? high current drive pin (for led). # pin not bonded on 42-pin sdip. 10-bit analog-to-digital converter module pulse width modulator module porta ddra pta5/atd7 ? pta0/atd2 ? ddrc portc ptc7/atd12 ? # ptc6/atd11 ? # ptc5/atd10 ? ptc4/atd9 ? ptc3/atd8 ? ptc2/pwm2 ptc1/pwm1 ptc0/pwm0/cd portd ddrd ptd7/kbi7 ? ptd0/kbi0 *** ** irq2 multi-master iic (smbus) interface module analog module opin1/atd0 # opin2/atd1 pta7/t1ch1 pta6/t1ch0 v ssam x-tal oscillator rc oscillator internal oscillator oscillators and
data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 40 general description freescale semiconductor general description 1.5 pin assignments figure 1-2. 48-pin lqfp pin assignments vssa 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 14 15 16 17 18 19 20 21 22 36 32 31 30 29 28 27 26 13 ptc3/atd8 irq1 ptd2/kbi2 rst nc ptd0/kbi0 vdd osc1 osc2 vss ptd1/kbi1 ptd4/kbi4 ptb2/sda1/txd ptb1/scl0 ptb0/sda0 ptb3/scl1/rxd ptd5/kbi5 ptc2/pwm2 ptc1/pwm1 ptc0/pwm0/cd pta7/t1ch1 ptd6/kbi6 opin2/atd1 vrefl vrefh opin1/atd0 vssam pta6/t1ch0 ptb6/irq2 ptb4/t2ch0 pta0/atd2 ptc7/atd12 ptb5/t2ch1 cgmxfc 12 ptd3/kbi3 25 ptd7/kbi7 11 24 nc 23 35 34 33 vdda ptc6/atd11 ptc5/atd10 ptc4/atd9 pta1/atd3 pta2/atd4 pta3/atd5 pta4/atd6 nc pta5/atd7 37 38 nc: no connection
general description pin functions mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor general description 41 figure 1-3. 42-pin sdip pin assignment 1.6 pin functions description of pin func tions are provided here. 21 22 ptd5/kbi5 ptd4/kbi4 ptc2/pwm2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 ptc1/pwm1 ptc0/pwm0/cd ptb2/sda1/txd ptb1/scl0 ptb0/sda0 ptc3/atd8 ptd2/kbi2 rst ptd3/kbi3 pta0/atd2 vrefl vrefh pta1/atd3 pta2/atd4 pta3/atd5 pta4/atd6 vssa ptb5/t2ch1 ptb4/t2ch0 ptd7/kbi7 pta6/t1ch0 ptb6/irq2 ptc5/atd10 vdda opin1/atd0 vssam ptc4/atd9 pta5/atd7 cgmxfc ptd0/kbi0 vdd osc1 osc2 vss ptd1/kbi1 irq1 pta7/t1ch1 20 23 ptd6/kbi6 ptb3/scl1/rxd pins not available on 42-pin package internal connection opin2/atd1 unconnected ptc6/atd11 unconnected ptc7/atd12 unconnected
data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 42 general description freescale semiconductor general description 1.6.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to preven t noise problems, take special care to provide power suppl y bypassing at the mcu as figure 1-4 shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response cerami c capacitor for c1. c2 is an optional bulk current bypa ss capacitor for use in appl ications that require the port pins to sour ce high current levels. figure 1-4. power supply bypassing v ss must be grounded for proper mcu operation. 1.6.2 oscillator pins (osc1 and osc2) the osc1 and osc2 pins ar e the connections for the on-chip oscillator circuit. see section 7. oscillator (osc) and section 8. clock generator module (cgm) . mcu v dd c2 c1 0.1 f v ss v dd + note: component values shown represent typical applications.
general description pin functions mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor general description 43 1.6.3 external reset pin (rst ) a logic 0 on the rst pin forces the mcu to a known start-up state. rst is bidirectional, allowing a reset of t he entire system. it is driven low when any internal reset source is asserted. this pin contains an internal pullup resistor. see section 9. system in tegration module (sim) . 1.6.4 external in terrupt pin (irq1 ) irq1 is an asynchronous external inte rrupt pin. this pi n contains an internal pullup resistor. see section 19. external interrupt (irq) . 1.6.5 analog power supply pin (v dda ) v dda is the power supply pin for t he analog circui ts of the mcu. 1.6.6 analog ground pin (v ssa ) v ssa is the power supply ground pin fo r the analog circuits of the mcu. it should be decoupl ed as per the v ss digital ground pin. 1.6.7 adc voltage low reference pin (v refl ) v refl is the voltage input pin for t he adc voltage low reference. see section 15. analog-to-dig ital converter (adc) . 1.6.8 adc voltage high reference pin (v refh ) v refh is the voltage input pin for the adc voltage high reference. see section 15. analog-to-dig ital converter (adc) . 1.6.9 external filter capacitor pin (cgmxfc) cgmxfc is an external filter capacito r connection for the cgm. see section 8. clock gene rator module (cgm) .
data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 44 general description freescale semiconductor general description 1.6.10 analog input pins (o pin1/atd0, opin2/atd1, v ssam ) opin1/atd0 and opin2/atd1 are input pins to the analog module and adc and v ssam is the negative re ference input. see section 14. analog module and section 15. anal og-to-digital converter (adc) . 1.6.11 port a input/ou tput (i/o) pins (pta7 ? pta0) pta7?pta0 are special functi on, bidirectional port pins. pta7/t1ch1?pta6/t1ch0 are shared with the tim1, and pta5/atd7?pta0/atd2 are shared with t he adc. see section 18. input/output (i/o) ports , section 11. timer in terface module (tim) , and section 15. analog-to-dig ital converter (adc) . 1.6.12 port b i /o pins (ptb6?ptb0) ptb6?ptb0 are special function, bidirectional port pins. ptb6/irq2 is shared with the irq2 input, ptb5/t 2ch1?ptb4/t2ch0 are shared with the tim2, ptb3/scl1/rxd?ptb2/s da1/txd are shared with the mmiic and sci, and pt b1/scl0?ptb0/sda0 ar e shared with the mmiic. see section 18. input/ou tput (i/o) ports , section 19. external interrupt (irq) , section 11. timer in terface module (tim) , section 16. serial comm unications interface (sci) , and section 17. multi-master iic interface (mmiic) . 1.6.13 port c i /o pins (ptc7?ptc0) ptc7?ptc0 are special functi on, bidirectional port pins. ptc7/atd12?ptc3/atd8 ar e shared with the adc, ptc2/pwm2?ptc1/pwm1 are sh ared with t he pwm, and ptc0/pwm0/cd is shared with the pwm and analog module. see section 18. input/output (i/o) ports , section 15. anal og-to-digital converter (adc) , section 13. pulse wi dth modulator (pwm) , and section 14. analog module . 1.6.14 port d i/o pi ns (ptd7/kbi7?ptd0/kbi0) ptd7?ptd0 are general-purpose bidirect ional port pins with keyboard wakeup function. see section 18. input/output (i/o) ports and section 20. keyboard in terrupt module (kbi) .
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor memory map 45 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.3 unimplemented memory loc ations . . . . . . . . . . . . . . . . . . . . . 45 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.2 introduction the cpu08 can address 64k-bytes of memory space. the memory map, shown in figure 2-1 , includes: 12,288 bytes of user flash memory 512 bytes of random-access memory (ram) 38 bytes of user-defined vectors 368 bytes of monitor rom 2.3 unimplemented memory locations accessing an unimplemented locati on can cause an illegal address reset. in the memory map ( figure 2-1 ) and in register figures in this document, unimplemented locations are shaded.
memory map data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 46 memory map freescale semiconductor 2.4 reserved memory locations accessing a reserved location can hav e unpredictable effects on mcu operation. in the figure 2-1 and in register figures in this document, reserved locations are marked with the word reserv ed or with the letter r. 2.5 input/output (i/o) section most of the control, status, and data register s are in the zero page $0000?$005f. additional i/o register s have the following addresses: $fe00; sim break st atus register, sbsr $fe01; sim reset st atus register, srsr $fe03; sim break flag control register, sbfcr $fe04; interrupt stat us register 1, int1 $fe05; interrupt stat us register 2, int2 $fe06; interrupt stat us register 3, int3 $fe07; reserved $fe08; flash contro l register, flcr $fe09; flash block protect register, flbpr $fe0a; reserved $fe0b; reserved $fe0c; break address register high, brkh $fe0d; break address register low, brkl $fe0e; break status and control register, brkscr $fe0f; lvi status register, lvisr $ff80; mask option register, mor $ffff; cop control register, copctl data registers are shown in figure 2-2 , table 2-1 is a list of vector locations.
memory map input/output (i/o) section mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor memory map 47 $0000 $005f i/o registers 96 bytes $0060 $025f ram 512 bytes $0260 $bfff unimplemented 48,544 bytes $c000 $efff flash memory 12,288 bytes $f000 $fdff unimplemented 3,584 bytes $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $fe06 interrupt status register 3 (int3) $fe07 reserved $fe08 flash control register (flcr) $fe09 flash block prot ect register (flbpr) $fe0a reserved $fe0b reserved $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and control register (brkscr) $fe0f lvi status register (lvisr) $fe10 $ff7f monitor rom 368 bytes $ff80 mask option register $ff81 $ffd9 reserved 89 bytes $ffda $ffff flash vectors 38 bytes figure 2-1. memory map
memory map data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 48 memory map freescale semiconductor addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset:uuuuuuuu $0001 port b data register (ptb) read: 0 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset:0uuuuuuu $0002 port c data register (ptc) read: ptc7 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset:uuuuuuuu $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset:uuuuuuuu $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: 0 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 unimplemented read: write: reset: $0009 unimplemented read: write: reset: u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 1 of 12)
memory map input/output (i/o) section mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor memory map 49 $000a unimplemented read: write: reset: $000b unimplemented read: write: reset: $000c port-a led control register (leda) read: 0 0 leda5 leda4 leda3 leda2 leda1 leda0 write: reset:00000000 $000d port-c led control register (ledc) read: ledc7 ledc6 ledc5 ledc4 ledc3 000 write: reset:00000000 $000e analog module control register (amcr) read: pwr1 pwr0 opch1 opch0 amien do2 do1 do0 write: reset:00000000 $000f analog module gain control register (amgcr) read: gainb3 gainb2 gainb1 gainb0 gaina3 gaina2 gaina1 gaina0 write: reset:00000000 $0010 analog module status and control register (amscr) read: amcdiv1 amcdiv0 0 opif 0 dof 0 cdif write: opifr cdifr reset:00u000u0 $0011 unimplemented read: write: reset: $0012 unimplemented read: write: reset: $0013 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 2 of 12)
memory map data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 50 memory map freescale semiconductor $0014 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 sci control register 3 (scc3) read: r8 t8 dmare dmate orie neie feie peie write: reset:uu000000 $0016 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 sci status register 2 (scs2) read: 000000bkfrpf write: reset:00000000 $0018 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:uuuuuuuu $0019 sci baud rate register (scbr) read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:0000 000 $001a keyboard status and control register (kbscr) read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $001c irq2 status and control register (intscr2) read: 0 ptbpue6 00irq2f0 imask2 mode2 write: ack2 reset:00000000 $001d configuration register 2 (config2) ? read: stop_ iclken stop_ rclken stop_ xclken oscclk1 oscclk0 0 cdoen scibdsrc write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 3 of 12)
memory map input/output (i/o) section mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor memory map 51 $001e irq1 status and control register (intscr1) read: 0000irq1f0 imask1 mode1 write: ack1 reset:00000000 $001f configuration register 1 (config1) ? read: coprs lvistop lvirstd lvipwrd lvi5or3 ssrec stop copd write: reset:00000000 ? one-time writable register after each reset. $0020 timer 1 status and control register (t1sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 timer 1 counter register high (t1cnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0022 timer 1 counter register low (t1cntl) read: bit 7 654321bit 0 write: reset:00000000 $0023 timer 1 counter modulo register high (t1modh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0024 timer 1 counter modulo register low (t1modl) read: bit 7654321bit 0 write: reset:11111111 $0025 timer 1 channel 0 status and control register (t1sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 timer 1 channel 0 register high (t1ch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:xxxxxxxx addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 4 of 12)
memory map data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 52 memory map freescale semiconductor $0027 timer 1 channel 0 register low (t1ch0l) read: bit 7654321bit 0 write: reset:xxxxxxxx $0028 timer 1 channel 1 status and control register (t1sc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 timer 1 channel 1 register high (t1ch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:xxxxxxxx $002a timer 1 channel 1 register low (t1ch1l) read: bit 7654321bit 0 write: reset:xxxxxxxx $002b timer 2 status and control register (t2sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $002c timer 2 counter register high (t2cnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $002d timer 2 counter register low (t2cntl) read: bit 7 654321bit 0 write: reset:00000000 $002e timer 2 counter modulo register high (t2modh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $002f timer 2 counter modulo register low (t2modl) read: bit 7654321bit 0 write: reset:11111111 $0030 timer 2 channel 0 status and control register (t2sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 5 of 12)
memory map input/output (i/o) section mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor memory map 53 $0031 timer 2 channel 0 register high (t2ch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:xxxxxxxx $0032 timer 2 channel 0 register low (t2ch0l) read: bit 7654321bit 0 write: reset:xxxxxxxx $0033 timer 2 channel 1 status and control register (t2sc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0034 timer 2 channel 1 register high (t2ch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:xxxxxxxx $0035 timer 2 channel 1 register low (t2ch1l) read: bit 7654321bit 0 write: reset:xxxxxxxx $0036 pll control register (ptcl) read: pllie pllf pllon bcs pre1 pre0 vpr1 vpr0 write: reset:00100000 $0037 pll bandwidth control register (pbwc) read: auto lock acq 0000 r write: reset:0000000 $0038 pll multiplier select register high (pmsh) read: 0000 mul11 mul10 mul9 mul8 write: reset:00000000 $0039 pll multiplier select register low (pmsl) read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 $003a pll vco range select register (pmrs) read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 6 of 12)
memory map data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 54 memory map freescale semiconductor $003b pll reference divider select register (pmds) read: 0000 rds3 rds2 rds1 rds0 write: reset: 0 00 0 0001 $003c unimplemented read: write: reset: $003d unimplemented read: write: reset: $003e unimplemented read: write: reset: $003f unimplemented read: write: reset: $0040 unimplemented read: write: reset: $0041 unimplemented read: write: reset: $0042 unimplemented read: write: reset: $0043 unimplemented read: write: reset: $0044 unimplemented read: write: reset: addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 7 of 12)
memory map input/output (i/o) section mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor memory map 55 $0045 unimplemented read: write: reset: $0046 timebase control register (tbcr) read: tbif tbr2 tbr1 tbr0 0 tbie tbon r write: tac k reset:0000000 $0047 unimplemented read: write: reset: $0048 mmiic address register (mmadr) read: mmad7 mmad6 mmad5 mmad4 mmad3 mmad2 mmad1 mmextad write: reset:10100000 $0049 mmiic control register 1 (mmcr1) read: mmen mmien 00 mmtxak repsen mmcrcbyte sdascl1 write: mmclrbb reset:00000000 $004a mmiic control register 2 (mmcr2) read: mmalif mmnakif mmbb mmast mmrw 00 mmcrcef write: 0 0 reset:0000000 unaffected $004b mmiic status register (mmsr) read: mmrxif mmtxif mmatch mmsrw mmrxak mmcrcbf mmtxbe mmrxbf write: 0 0 reset:00001010 $004c mmiic data transmit register (mmdtr) read: mmtd7 mmtd6 mmtd5 mmtd4 mmtd3 mmtd2 mmtd1 mmtd0 write: reset:00000000 $004d mmiic data receive register (mddrr) read: mmrd7 mmrd6 mmrd5 mmr d4 mmrd3 mmrd2 mmrd1 mmrd0 write: reset:00000000 $004e mmiic crc data register (mmcrdr) read: mmcrcd7 mmcrcd6 mmcrcd5 mmcrcd4 mmcrcd3 mmcrcd2 mmcrcd1 mmcrcd0 write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 8 of 12)
memory map data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 56 memory map freescale semiconductor $004f mmiic frequency divider register (mmfdr) read: 00000 mmbr2 mmbr1 mmbr0 write: reset:00000100 $0050 reserved read: rrrrrrrr write: reset: $0051 pwm control register (pwmcr) read: pwmen2 pwmen1 pwmen0 00 pch2 pch1 pch0 write: reset:00000000 $0052 pwm clock control register (pwmccr) read: pclksel 00000 pclk1 pclk0 write: reset:00000000 $0053 pwm data register 0 (pwmdr0) read: 0pwmd7 0pwmd6 0pwmd5 0pwmd4 0pwmd3 0pwmd2 0pwmd1 0pwmd0 write: reset:00000000 $0054 pwm data register 1 (pwmdr1) read: 1pwmd7 1pwmd6 1pwmd5 1pwmd4 1pwmd3 1pwmd2 1pwmd1 1pwmd0 write: reset:00000000 $0055 pwm data register 2 (pwmdr2) read: 2pwmd7 2pwmd6 2pwmd5 2pwmd4 2pwmd3 2pwmd2 2pwmd1 2pwmd0 write: reset:00000000 $0056 pwm phase control register (pwmpcr) read: phen phd6 phd5 phd4 phd3 phd2 phd1 phd0 write: reset:00000000 $0057 adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $0058 adc clock control register (adiclk) read: adiv2 adiv1 adiv0 adiclk mode1 mode0 00 write: r reset:00000100 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 9 of 12)
memory map input/output (i/o) section mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor memory map 57 $0059 adc data register high 0 (adrh0) read: adx adx adx adx adx adx adx adx write:rrrrrrrr reset:00000000 $005a adc data register low 0 (adrl0) read: adx adx adx adx adx adx adx adx write:rrrrrrrr reset:00000000 $005b adc data register low 1 (adrl1) read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset:00000000 $005c adc data register low 2 (adrl3) read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset:00000000 $005d adc data register low 3 (adrl3) read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset:00000000 $005e adc auto-scan control register (adascr) read: 00000 auto1 auto0 ascan write: reset:00000000 $005f unimplemented read: write: reset: $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 note: writing a l ogic 0 clears sbsw. $fe01 sim reset status register (srsr) read: por pin cop ilop ilad 0 lvi 0 write: por:10000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data regi sters (sheet 10 of 12)
memory map data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 58 memory map freescale semiconductor $fe02 reserved read: rrrrrrrr write: reset: $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) read: 00000if17if16if15 write:rrrrrrrr reset:00000000 $fe07 reserved read: rrrrrrrr write: reset: $fe08 flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe09 flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 $fe0a reserved read: rrrrrrrr write: reset: $fe0b reserved read: rrrrrrrr write: reset: addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data regi sters (sheet 11 of 12)
memory map input/output (i/o) section mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor memory map 59 $fe0c break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 $fe0f low-voltage inhibit status register (lvisr) read: lviout 0000000 write: reset:00000000 $ff80 mask option register (mor)* read: oscsel1oscsel0rrrrrr write: erased:11111111 reset:uuuuuuuu * mor is a non-volatile flash register; write by programming. $ffff cop control register (copctl) read: low byte of reset vector write: writing clears co p counter (any value) reset:uuuuuuuu addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data regi sters (sheet 12 of 12)
memory map data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 60 memory map freescale semiconductor . table 2-1. vector addresses vector priority vector address vector lowest if17 $ffda timebase module interrupt vector (high) $ffdb timebase module interrupt vector (low) if16 $ffdc analog module interrupt vector (high) $ffdd analog module interrupt vector (low) if15 $ffde adc conversion co mplete vector (high) $ffdf adc conversion complete vector (low) if14 $ffe0 keyboard vector (high) $ffe1 keyboard vector (low) if13 $ffe2 sci transmit vector (high) $ffe3 sci transmit vector (low) if12 $ffe4 sci receive vector (high) $ffe5 sci receive vector (low) if11 $ffe6 sci error vector (high) $ffe7 sci error vector (low) if10 $ffe8 mmiic interrupt vector (high) $ffe9 mmiic interrupt vector (low) if9 $ffea tim2 overflow vector (high) $ffeb tim2 overflow vector (low) if8 $ffec tim2 channel 1 vector (high) $ffed tim2 channel 1 vector (low) if7 $ffee tim2 channel 0 vector (high) $ffef tim2 channel 0 vector (low) if6 $fff0 tim1 overflow vector (high) $fff1 tim1 overflow vector (low) if5 $fff2 tim1 channel 1 vector (high) $fff3 tim1 channel 1 vector (low) if4 $fff4 tim1 channel 0 vector (high) $fff5 tim1 channel 0 vector (low) if3 $fff6 pll vector (high) $fff7 pll vector (low) if2 $fff8 irq2 vector (high) $fff9 irq2 vector (low) if1 $fffa irq1 vector (high) $fffb irq1 vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) highest $ffff reset vector (low)
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor random-access memory (ram) 61 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3.2 introduction this section describes the 512 by tes of ram (random-access memory). 3.3 functional description addresses $0060 through $0 25f are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64k-byte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 160 bytes of ra m. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff out of page zero, direct addressing mode instructions can efficiently acce ss all page zero ram locations. page zero ram, therefore, provides i deal locations for frequently accessed global variables. before processing an interrupt, the cp u uses five bytes of the stack to save the contents of the cpu registers. note: for m6805 compatibility, the h register is not stacked.
random-access memory (ram) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 62 random-access memory (ram) freescale semiconductor during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack po inter decrements during pushes and increments during pulls. note: be careful when using nested subr outines. the cpu ma y overwrite data in the ram during a s ubroutine or during the interrupt stacking operation.
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor flash memory 63 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 4. flash memory 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.5 flash page erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .68 4.8 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.8.1 flash block protect regi ster . . . . . . . . . . . . . . . . . . . . . . . 70 4.2 introduction this section describes the operat ion of the embedd ed flash memory. this memory can be r ead, programmed, and er ased from a single external supply. the program and er ase operations are enabled through the use of an internal charge pump.
flash memory data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 64 flash memory freescale semiconductor 4.3 functional description the flash memory consists of an array of 12,288 bytes for user memory plus a block of 38 bytes fo r user interrupt vectors and one byte for the mask op tion register. an erased bit reads as logic 1 and a programmed bit reads as a logic 0 . the flash memory page size is defined as 128 bytes, and is the mini mum size that can be erased in a page erase operation. program and er ase operations ar e facilitated through control bits in flash co ntrol register (flcr). the address ranges for the flash memory are: $c000?$efff; user me mory, 12,288 bytes $ffda?$ffff; user interr upt vectors, 38 bytes $ff80; mask option register programming tools are available from freescale. contact your local freescale representative for more information. note: a security feature prevents vi ewing of the flash contents. 1 addr.register name bit 7654321bit 0 $fe08 flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe09 flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 = unimplemented figure 4-1. flash i/ o register summary 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users.
flash memory flash control register mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor flash memory 65 4.4 flash control register the flash control register (flcr) controls flash program and erase operations. hven ? high voltage enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operati ons in the array. hv en can only be set if either pgm = 1 or erase = 1 and t he proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit this read/write bit confi gures the memory for mass erase operation or block erase operation when the erase bit is set. 1 = mass erase operation selected 0 = block erase operation selected erase ? erase control bit this read/write bit conf igures the memory for erase operation. erase is interlocked wit h the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation not selected pgm ? program control bit this read/write bit conf igures the memory fo r program operation. pgm is interlocked with the erase bit such t hat both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation not selected address: $fe08 bit 7654321bit 0 read: 0000 hven mass erase pgm write: reset:00000000 figure 4-2. flash cont rol register (flcr)
flash memory data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 66 flash memory freescale semiconductor 4.5 flash page erase operation use the following procedure to er ase a page of flash memory. a page consists of 128 consecutive bytes starting from addresses $xx00 or $xx80. the 38-byte user interrupt vectors area also forms a page. the 38-byte user interrupt vectors c annot be erased by the page erase operation because of security reasons. mass erase is required to erase this page. 1. set the erase bit and clear the mass bit in th e flash control register. 2. write any data to any flash address within the page address range desired. 3. wait for a time, t nvs (10 s). 4. set the hven bit. 5. wait for a time, t erase (1ms). 6. clear the erase bit. 7. wait for a time, t nvh (5 s). 8. clear the hven bit. 9. after time, t rcv (1 s), the memory can be accessed again in read mode. note: programming and erasing of flash locations c annot be performed by executing code from the flash me mory; the code must be executed from ram. while these operations must be perfo rmed in the order as shown, but other unre lated operations may occur between the steps.
flash memory flash mass erase operation mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor flash memory 67 4.6 flash mass erase operation use the following procedure to erase the entire flash memory to read as logic 1: 1. set both the erase bit and the mass bit in the flash control register. 2. write any data to any flash address within the flash memory address range. 3. wait for a time, t nvs (10 s). 4. set the hven bit. 5. wait for a time t merase (4ms). 6. clear the erase bit. 7. wait for a time, t nvhl (100 s). 8. clear the hven bit. 9. after time, t rcv (1 s), the memory can be accessed again in read mode. note: programming and erasing of flash locations c annot be performed by executing code from the flash me mory; the code must be executed from ram. while these operations must be perfo rmed in the order as shown, but other unre lated operations may occur between the steps.
flash memory data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 68 flash memory freescale semiconductor 4.7 flash program operation programming of the flash memory is done on a row basis. a row consists of 64 consecutive bytes st arting from addresses $xx00, $xx40, $xx80, or $xxc0. the procedure for programmi ng a row of the flash memory is outlined below: 1. set the pgm bit. this configur es the memory for program operation and enables the latchi ng of address and data for programming. 2. write any data to any flash address within t he row address range desired. 3. wait for a time, t nvs (10 s). 4. set the hven bit. 5. wait for a time, t pgs (5 s). 6. write data to the flash address to be programmed. 7. wait for time, t prog (30 s). 8. repeat step 6 and 7 until all the bytes within the row are programmed. 9. clear the pgm bit. 10. wait for time, t nvh (5 s). 11. clear the hven bit. 12. after time, t rcv (1 s), the memory can be ac cessed again in read mode. this program sequence is repeated th roughout the memory until all data is programmed. note: programming and erasing of flash locations c annot be performed by executing code from the flash me mory; the code must be executed from ram. while these operations must be perfo rmed in the order as shown, but other unrelated operations may occur between the steps. do not exceed t prog maximum. see 24.18 flash memory characteristics .
flash memory flash program operation mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor flash memory 69 figure 4-3 shows a flowchart represen tation for programming the flash memory. figure 4-3. flash programming flowchart set hven bit write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 6 to step 6), or must not exceed the maximum programming time, t prog max. the time between the last flash address programmed to clearing pgm bit (step 6 to step 9) note: 1 2 3 4 5 6 7 9 10 11 12 algorithm for programming a row (64 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased.
flash memory data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 70 flash memory freescale semiconductor 4.8 flash protection due to the ability of the on-board charge pump to erase and program the flash memory in the tar get application, provis ion is made to protect pages of memory from unintentional er ase or program operations due to system malfunction. this protection is done by use of a flash block protect register (flb pr). the flbpr determine s the range of the flash memory which is to be prot ected. the range of the protected area starts from a location defined by flbpr and ends to the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or prog ram operations. note: when the flbpr is cleared (all 0?s) , the entire flash memory is protected from being prog rammed and erased. when all the bits are set, the entire flash memory is a ccessible for program and erase. 4.8.1 flash bloc k protect register the flash block protect regi ster is implemented as an 8-bit i/o register. the content of this regi ster determine the sta rting location of the protected range within the flash memory. bpr[7:0] ? flash blo ck protect register bit7 to bit 0 bpr[7:1] represent bits [13:7] of a 16-bit memory address. bits [15:14] are logic 1s and bits [6:0] are logic 0s. figure 4-5. flash block protect start address address: $fe09 bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 figure 4-4. flash block pr otect register (flbpr) 16-bit memory address start address of flash block protect 11 0000000 bpr[7:1]
flash memory flash protection mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor flash memory 71 bpr0 is used only for bpr[7:0] = $ff, for no block protection. the resultant 16-bit address is used for specifying the start address of the flash memory for block pr otection. the flash is protected from this start address to the end of flash me mory, at $ffff. with this mechanism, the protect star t address can be xx00 or xx80 (at page boundaries) within the flash memory. examples of protect start address: bpr[7:0] start of address of protect range $00 or $01 $c000 (11 00 0000 0 000 0000) the entire flash memory is protected. $02 or $03 $c080 (11 00 0000 1 000 0000) $04 or $05 $c100 (11 00 0001 0 000 0000) $06 or $07 $c180 (11 00 0001 1 000 0000) $08 or $09 $c200 (11 00 0010 0 000 0000) and so on... $f8 or $f9 $fe00 (11 11 1110 0 000 0000) $fa or $fb $fe80 (11 11 1110 1 000 0000) $fc or $fd $ff00 (11 11 1111 0 000 0000) $fe $ff80 (11 11 1111 1 000 0000) $ff the entire flash memory is not protected. note: the end address of the protected range is always $ffff.
flash memory data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 72 flash memory freescale semiconductor
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor configuration and mask option registers (config & mor) 73 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 5. configurati on and mask option registers (config & mor) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 5.4 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . . 75 5.5 configuration register 2 (config2) . . . . . . . . . . . . . . . . . . . . 77 5.6 mask option register (mor) . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2 introduction this section describes the config uration registers, config1 and config2; and the mask option register, mor. the configuration registers enabl e or disable these options: computer operating pr operly module (cop) cop timeout period (2 18 ? 2 4 or 2 13 ? 2 4 iclk cycles) low-voltage inhibi t (lvi) module power lvi module reset lvi module in stop mode lvi module voltage trip point selection stop instruction stop mode recovery time (32 iclk cycles or 4096 iclk cycles) oscillator (internal, rc, a nd crystal) during stop mode serial communications interfac e clock source (cgmxclk or f bus ) current detec t output pin
configuration and mask option data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 74 configuration and mask option registers (config & mor) freescale semiconductor the mask option register selects one of the following oscillator options as the mcu reference clock: internal oscillator rc oscillator crystal oscillator 5.3 functional description the configuration register s and the mask option regi ster are used in the initialization of various options. these two types of registers are configured differently: configuration registers ? wr ite-once registers after reset mask option register ? flash r egister (write by programming) the configuration registers can be writ ten once after each reset. all of the configuration r egister bits are cleared durin g reset. since the various options affect the operat ion of the mcu, it is recommended that these registers be written imme diately after reset. the configuration registers are located at $001d and $001f. the configurati ons register may be read at anytime. addr.register name bit 7654321bit 0 $001d configuration register 2 (config2) ? read: stop_ iclken stop_ rclken stop_ xclken oscclk1 oscclk0 0 cdoen scibdsrc write: reset:00000000 $001f configuration register 1 (config1) ? read: coprs lvistop lvirstd lvipwrd lvi5or3 ssrec stop copd write: reset:00000 ?? 000 $ff80 mask option register (mor)* read: oscsel1oscsel0rrrrrr write: erased:11111111 * flash register. reset:uuuuuuuu ? one-time writable register after each reset. ?? reset by por only. = unimplemented r = reserved figure 5-1. config and mor register summary
configuration and mask option registers (config & mor) configuration register 1 (config1) mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor configuration and mask option registers (config & mor) 75 note: the options except lvi5 or3 are one-time writabl e by the user after each reset. the lv i5or3 bit is one-ti me writable by the user only after each por (power-on rese t). the config regist ers are not in the flash memory but are special regist ers containing on e-time writable latches after each reset. upon a reset, the config registers default to predetermined settings as shown in figure 5-2 and figure 5-3 . the mask option register (mor) is us ed for selecting on e of the three clock options for the mcu. the mor is a by te located in flash memory, and is written to by a flash programming routine. 5.4 configuration register 1 (config1) coprs ? cop rate select coprs selects the cop time-out period. reset clears coprs. (see section 21. computer o perating properly (cop) .) 1 = cop time out period = 2 13 ? 2 4 iclk cycles 0 = cop time out period = 2 18 ? 2 4 iclk cycles lvistop ? lvi enable in stop mode when the lvipwrd bit is clear, se tting the lvistop bit enables the lvi to operate during stop mode . reset clears lvistop. (see section 22. low-vol tage inhibit (lvi) .) 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode address: $001f bit 7654321bit 0 read: coprs lvistop lvirstd lvipwrd lvi5or3 ssrec stop copd write: reset:00000*000 * reset by por only. figure 5-2. configuratio n register 1 (config1)
configuration and mask option data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 76 configuration and mask option registers (config & mor) freescale semiconductor lvirstd ? lvi reset disable lvirstd disables the reset signa l from the lvi module. (see section 22. low-vol tage inhibit (lvi) .) 1 = lvi module resets disabled 0 = lvi module resets enabled lvipwrd ? lvi power disable bit lvipwrd disables the lvi module. (see section 22. low-voltage inhibit (lvi) .) 1 = lvi module power disabled 0 = lvi module power enabled lvi5or3 ? lvi 5v or 3v operating mode lvi5or3 selects the voltage operati ng mode of the lvi module. (see section 22. low-voltage inhibit (lvi) .) the voltage mode selected for the lvi should ma tch the operating v dd . see section 24. electrical specifications for the lvi voltage trip points for each of the modes. 1 = lvi operates in 5v mode 0 = lvi operates in 3v mode ssrec ? short stop recovery ssrec enables the cpu to exit stop mode with a delay of 32 iclk cycles instead of a 4096 iclk cycle delay. 1 = stop mode recovery after 32 iclk cycles 0 = stop mode recovery after 4096 iclk cycles note: exiting stop mode by pulling reset will result in the long stop recovery. if using an external crystal oscillat or, and it is dis abled during stop mode (stop_xclken=0), do not set the ssrec bit. note: when the lvi is disabled in st op mode (lvistop=0), the system stabilization time for l ong stop recovery (4096 iclk cycles) gives a delay longer than the lvi?s turn-on time. there is no period where the mcu is not protected from a low power c ondition. however, when using the short stop recovery conf iguration option, the 32 iclk delay is less than the lvi?s turn-on time and there exists a period in start-up where the lvi is not protec ting the mcu.
configuration and mask option registers (config & mor) configuration register 2 (config2) mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor configuration and mask option registers (config & mor) 77 stop ? stop instruction enable stop enables the stop instruction. 1 = stop inst ruction enabled 0 = stop instruction tr eated as illegal opcode copd ? cop disable bit copd disables the cop module. (see section 21. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled 5.5 configuration register 2 (config2) stop_iclken ? internal o scillator stop mode disable stop_iclken disables the inter nal oscillator du ring stop mode. setting the stop_iclken bit disa bles the oscillator during stop mode. (see 7.4 internal oscillator ). reset clears this bit. 1 = internal oscillator disabled during stop mode 0 = internal oscilla tor enabled to oper ate during stop mode stop_rclken ? rc oscill ator stop mode enable stop_rclken enables the rc osci llator to co ntinue operating during stop mode. setting the stop_rclken bit allows the oscillator to operat e continuously even du ring stop mode. this is useful for driving the timebase module to allow it to generate periodic wake up while in stop mode. (see section 8. clock generator module (cgm) and subsection 8.8.2 stop mode .) reset clears this bit. 1 = rc oscillator enabled to operat e during stop mode 0 = rc oscillator dis abled during stop mode address: $001d bit 7654321bit 0 read: stop_ iclken stop_ rclken stop_ xclken oscclk1 oscclk0 0 cdoen scibdsrc write: reset:00000000 figure 5-3. configuratio n register 2 (config2)
configuration and mask option data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 78 configuration and mask option registers (config & mor) freescale semiconductor stop_xclken ? crystal o scillator stop mode enable stop_xclken enables the crystal (x-tal) oscillator to continue operating during stop mode. settin g the stop_xclken bit allows the x-tal oscillator to operate continuously even during stop mode. this is useful for driving the tim ebase module to allow it to generate periodic wake up whil e in stop mode. (see section 8. clock generator module (cgm) and subsection 8.8.2 stop mode .) reset clears this bit. 1 = x-tal oscillat or enabled to operat e during stop mode 0 = x-tal oscillator di sabled during stop mode oscclk1, oscclk0 ? oscillat or output control bits oscclk1 and oscclk0 select which oscillator output to be driven out as oscclk to the timebase module (tbm). reset clears these two bits. cdoen ? current-flow detect output enable cdoen enables the port pin pc0/pwm0/ cd as the cd output pin for the current detect flag (cdif) fr om the analog modul e. reset clears the cdoen bit. 1 = pco/pwmo/cd pin enabl ed as cd output pin, ptc0 and pwm0 func tions are disabled. 0 = ptc0/pwm/cd pin di sabled as cd output pin, ptc0 or pwm0 functions are available; see 18.5.1 port c data register (ptc) . oscclk1 oscclk0 timebase clock source 0 0 internal oscillator (iclk) 0 1 rc oscillator (rcclk) 1 0 x-tal oscillator (xtal) 1 1 not used
configuration and mask option registers (config & mor) mask option register (mor) mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor configuration and mask option registers (config & mor) 79 scibdsrc ? sci baud rate clock source scibdsrc selects the cl ock source used for the sci. the setting of this bit affects the frequency at which the sci operates. 1 = internal dat a bus clock, f bus , is used as clock source for sci 0 = oscillator clock, cgmxclk, is used as clock source for sci 5.6 mask option register (mor) the mask option register (mor) is us ed for selecting on e of the three clock options for the mcu. the mor is a by te located in flash memory, and is written to by a flash programming routine. oscsel1, oscsel0 ? oscillator selection bits oscsel1 and oscsel0 select which o scillator is used for the mcu cgmxclk clock. the eras e state of these two bi ts is logic 1. these bits are unaffected by reset. (see table 5-1 ). bits 5?0 ? should be left as 1?s. address: $ff80 bit 7654321bit 0 read: oscsel1oscsel0rrrrrr write: erased:11111111 reset:uuuuuuuu r=reserved figure 5-4. mask op tion register (mor)
configuration and mask option data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 80 configuration and mask option registers (config & mor) freescale semiconductor note: the internal oscillator is a free runni ng oscillator and is available after each por or reset. it is turned-o ff in stop mode by clearing the stop_iclken bit in config2. table 5-1. cgmxclk clock selection oscsel1 oscsel0 cgmxclk osc2 pin comments 0 0 ? ? not used 01iclkf bus internal oscillator gen erates the cgmxclk. 1 0 rcclk f bus rc oscillator generates the cgmxclk. internal oscillator is av ailable after each por or reset. 11x-tal inverting output of xtal x-tal oscillator generates the cgmxclk. internal oscillator is av ailable after each por or reset.
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor central processor unit (cpu) 81 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 6. central processor unit (cpu) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 6.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.2 introduction the m68hc08 cpu (central proce ssor unit) is an enhanced and fully object-code-compatible vers ion of the m 68hc05 cpu. the cpu08 reference manual (freescale document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture.
central processor unit (cpu) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 82 central processor unit (c pu) freescale semiconductor 6.3 features object code fully upward-com patible with m68hc05 family 16-bit stack pointer with st ack manipulation instructions 16-bit index register with x-regi ster manipulation instructions 8-mhz cpu internal bus frequency 64k-byte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decim al (bcd) data handling modular architecture with exp andable internal bu s definition for extension of addressing range beyond 64k-bytes low-power stop and wait modes 6.4 cpu registers figure 6-1 shows the five cpu registers. cpu regist ers are not part of the memory map.
central processor unit (cpu) cpu registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor central processor unit (cpu) 83 figure 6-1. cpu registers 6.4.1 accumulator the accumulator is a general-purpose 8- bit register. the cpu uses the accumulator to hold operands and th e results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a)
central processor unit (cpu) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 84 central processor unit (c pu) freescale semiconductor 6.4.2 index register the 16-bit index register allows i ndexed addressing of a 64k-byte memory space. h is the upper byte of the index regi ster, and x is the lower byte. h:x is the conc atenated 16-bit index register. in the indexed addressi ng modes, the cpu uses the contents of the index register to determine the conditional addr ess of the operand. the index register can serve also as a temporary data storage location. 6.4.3 stack pointer the stack pointer is a 16-bi t register that contains the address of the next location on the stack. during a rese t, the stack pointer is preset to $00ff. the reset stack pointer (rsp ) instruction sets the least significant byte to $ff and does not af fect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bi t offset and 16-bit offs et addressing modes, the stack pointer can functi on as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. bit 15 1413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 6-3. index register (h:x)
central processor unit (cpu) cpu registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor central processor unit (cpu) 85 note: the location of the stack is arbitr ary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, t he stack pointer must point only to ram locations. 6.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter autom atically increm ents to the next sequential memory location every time an instruct ion or operand is fetched. jump, branch, and interr upt operations l oad the program counter with an addr ess other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vect or address is the address of the first instruction to be executed after exiti ng the reset state. 6.4.5 condition code register the 8-bit condition code register cont ains the interrupt mask and five flags that indicate the re sults of the instruction just executed. bits 6 and bit 15 1413121110987654321 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) bit 15 1413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. prog ram counter (pc)
central processor unit (cpu) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 86 central processor unit (c pu) freescale semiconductor 5 are set permanently to logic 1. the following paragraphs describe the functions of the cond ition code register. v ? overflow flag the cpu sets the overfl ow flag when a two's complement overflow occurs. the signed branch instructi ons bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry fl ag when a carry occurs between accumulator bits 3 and 4 during an add-without-car ry (add) or add- with-carry (adc) operat ion. the half-carry flag is required for binary- coded decimal (bcd) arithmetic oper ations. the daa instruction uses the states of the h and c flags to determine t he appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 6-6. condition code register (ccr)
central processor unit (cpu) cpu registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor central processor unit (cpu) 87 i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are ena bled when the interrupt mask is cleared. when a cpu in terrupt occurs, the interrupt mask is set automatically after t he cpu registers are sa ved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not sta cked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is clear ed, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instru ction pulls the cp u registers from the stack and restores the interr upt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmet ic operation, logic operation, or data manipul ation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulati on produces a result of $00. 1 = zero result 0 = non-zero result
central processor unit (cpu) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 88 central processor unit (c pu) freescale semiconductor c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.5 arithmetic/logic unit (alu) the alu performs the arit hmetic and logic operat ions defined by the instruction set. refer to the cpu08 reference manual (freescale document order number cpu08rm/ad) for a descripti on of the instructions and addressing modes and more detail about the architectu re of the cpu. 6.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.6.1 wait mode the wait instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock
central processor unit (cpu) cpu during break interrupts mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor central processor unit (cpu) 89 6.6.2 stop mode the stop instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. afte r exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, t he cpu clock begins running after the oscillator stabilization delay. 6.7 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction regist er with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and retu rns the mcu to normal operation if the break interrupt has been deasserted. 6.8 instruction set summary 6.9 opcode map see table 6-2 .
central processor unit (cpu) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 90 central processor unit (c pu) freescale semiconductor table 6-1. instr uction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) rr ? rrr imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) rr ? rrr imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? rr ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) r ?? rrr dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right r ?? rrr dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ? ? ? ? ? ? rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 c b0 b7 0 b0 b7 c
central processor unit (cpu) opcode map mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor central processor unit (cpu) 91 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ? ? ? ? ? ? rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? rr ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ? ? ? ? ? ? rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 92 central processor unit (c pu) freescale semiconductor brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? r dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? r dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) opcode map mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor central processor unit (cpu) 93 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) r ?? rrr imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? rr 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) r ?? rrr imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) r ?? rrr imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? rrr inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ?1 or m (m) ?1 or x (x) ?1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 r ?? rr ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? rr inh 52 7 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 94 central processor unit (c pu) freescale semiconductor eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? rr ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 r ?? rr ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? rr ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? rr ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? rr ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) r ?? rrr dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0
central processor unit (cpu) opcode map mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor central processor unit (cpu) 95 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right r ??0 rr dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? rr ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) r ?? rrr dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ? ? ? ? ? ? inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ? ? ? ? ? ? inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? rr ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry r ?? rrr dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c 0 c b0 b7
central processor unit (cpu) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 96 central processor unit (c pu) freescale semiconductor ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry r ?? rrr dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) rrrrrr inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) r ?? rrr imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? rr ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? rr ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ? ? 0 ? ? ? inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? rr ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c
central processor unit (cpu) opcode map mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor central processor unit (cpu) 97 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) r ?? rrr imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) rrrrrr inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ? ? ? ? ? ? inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? rr ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 98 central processor unit (c pu) freescale semiconductor a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with post increment addressi ng mode rr relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack point er 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increm ent to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, post increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location r set or cleared n negative bit ? not affected table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor central processor unit (cpu) 99 central processor unit (cpu) opcode map table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789abcd9ede9eef 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4sp2 3 sub 2ix1 4 sub 3sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4sp2 3 cmp 2ix1 4 cmp 3sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4sp2 3 sbc 2ix1 4 sbc 3sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4sp2 3 cpx 2ix1 4 cpx 3sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4sp2 3 and 2ix1 4 and 3sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4sp2 3 bit 2ix1 4 bit 3sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4sp2 3 lda 2ix1 4 lda 3sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4sp2 3 sta 2ix1 4 sta 3sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4sp2 3 eor 2ix1 4 eor 3sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4sp2 3 adc 2ix1 4 adc 3sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4sp2 3 ora 2ix1 4 ora 3sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4sp2 3 add 2ix1 4 add 3sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4sp2 3 ldx 2ix1 4 ldx 3sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4sp2 3 stx 2ix1 4 stx 3sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb
central processor unit (cpu) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 100 central processor unit (cpu) freescale semiconductor
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconduc tor oscillator (osc) 101 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 7. oscillator (osc) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.3 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.3.1 cgm reference clock selection . . . . . . . . . . . . . . . . . . . . 104 7.3.2 tbm reference clock selection . . . . . . . . . . . . . . . . . . . . 105 7.4 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.5 rc oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.6 x-tal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.7.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . 108 7.7.2 crystal amplifier ou tput pin (osc2) . . . . . . . . . . . . . . . . . 109 7.7.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . 109 7.7.4 cgm oscillator clock (cgmxclk) . . . . . . . . . . . . . . . . . . 109 7.7.5 cgm reference clock (cgmrclk) . . . . . . . . . . . . . . . . . 109 7.7.6 oscillator clock to time base module (oscclk) . . . . . . . 109 7.8 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 7.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 7.9 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . 110
oscillator (osc) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 102 oscillator (osc) freescale semiconductor 7.2 introduction the oscillator module provides t he reference clock for the clock generator module (cgm), the timebase module (t bm), and other mcu sub-systems. the oscillator module consist of thre e types of oscill ator circuits: internal oscillator rc oscillator crystal (x-tal) oscillator the reference clock for the cgm and other mcu sub-systems is selected by: mc68hc908sr12 ? flash device ? oscillator selected by programming the mask option r egister located at $ff80. mc68hc08sr12 ? rom device ? oscillator selected by rom- mask layer at factory. the reference clock for the timebase m odule (tbm) is selected by the two bits, oscclk1 and oscclk0, in the config2 register. the internal oscillator runs conti nuously after a por or reset, and is always available. the rc and crystal o scillator cannot run concurrently; one is disabled while the other is selected; because the rc and x-tal circuits share the same osc1 pin. figure 7-1 . shows the block diagram of the oscillator module.
oscillator (osc) clock selection mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconduc tor oscillator (osc) 103 figure 7-1. oscillator module block diagram 7.3 clock selection reference clocks are selectable for the following sub-systems: cgmxclk and cgmrclk ? re ference clock for clock generator module (cgm) and other mcu sub-systems other than tbm and cop. this is the main reference clock for the mcu. oscclk ? reference clock for timebase module (tbm). x-tal oscillator rc oscillator internal oscillator mux osc1 osc2 bus clock from sim mux xclk rcclk iclk oscclk0 oscclk1 oscsel0 oscsel1 oscclk to tbm cgmxclk cgmrclk to cgm and others mor config2 to cgm pll xrci xrci to sim (and cop)
oscillator (osc) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 104 oscillator (osc) freescale semiconductor 7.3.1 cgm refere nce clock selection the clock generator module (cgm) reference clo ck (cgmxclk) is the reference clock input to the mcu. it is selected by programming two bits in a flash memory location; the mask option register (m or), at $ff80. see 5.6 mask option register (mor) . note: on the rom device, the oscillator is selected by a rom-mask layer at factory. note: the internal oscillator is a free runni ng oscillator and is available after each por or reset. it is turned-o ff in stop mode by clearing the stop_iclken bit in config2. address: $ff80 bit 7654321bit 0 read: oscsel1oscsel0rrrrrr write: erased:11111111 reset:uuuuuuuu r=reserved figure 7-2. mask op tion register (mor) table 7-1. cgmxclk clock selection oscsel1 oscsel0 cgmxclk osc2 pin comments 0 0 ? ? not used 01iclkf bus internal oscillator gen erates the cgmxclk. 1 0 rcclk f bus rc oscillator generates the cgmxclk. internal oscillator is av ailable after each por or reset. 11xclk inverting output of x-tal x-tal oscillator generates the cgmxclk. internal oscillator is av ailable after each por or reset.
oscillator (osc) internal oscillator mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconduc tor oscillator (osc) 105 7.3.2 tbm refer ence clock selection the timebase module reference cl ock (oscclk) is selected by configuring two bits in the config2 register, at $001d. see 5.5 configuration regi ster 2 (config2) . note: the rcclk or xclk is only available if that clock is selected as the cgm reference clock, whereas the iclk is always available. 7.4 internal oscillator the internal oscillator clock (iclk) is a free running 24khz clock that requires no external components. it can be selected as the cgmxclk for the cgm and mcu sub-systems ; and the oscclk clock for the tbm. the iclk is also the refere nce clock input to the computer operating properly (cop) module. due to the simplicity of the internal oscillator , it does not have the accuracy and stability of the rc o scillator or the x-tal oscillator. therefore, the iclk is not suitable where an accurate bus clock is required and it should not be used as the cgmr clk to the cgm pll. address: $001d bit 7654321bit 0 read: stop_ iclken stop_ rclken stop_ xclken oscclk1 oscclk0 0 cdoen scibdsrc write: reset:00000000 figure 7-3. configuratio n register 2 (config2) table 7-2. timebase module reference clock selection oscclk1 oscclk0 timebase clock source 0 0 internal oscillator (iclk) 0 1 rc oscillator (rcclk) 1 0 x-tal oscillator (xclk) 1 1 not used
oscillator (osc) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 106 oscillator (osc) freescale semiconductor the internal oscillator by default is always available and is free running after por or reset. it can be stopped in st op mode by setting the stop_iclken bit before execut ing the stop instruction. figure 7-4 shows the logical represent ation of components of the internal oscillator circuitry. figure 7-4. internal oscillator 7.5 rc oscillator the rc oscillator circuit is designed for use with external r and c to provide a clock source with tolerance less than 10%. in its typical configur ation, the rc oscillator requires two external components, one r and one c. compo nent values should have a tolerance of 1% or less, to obtain a clock source with less than 10% tolerance. the oscillator conf iguration uses two components: c ext r ext internal oscillator en simoscen stop_iclken config2 iclk mcu from sim to clock selection mux bus clock from sim osc2 and cop
oscillator (osc) x-tal oscillator mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconduc tor oscillator (osc) 107 figure 7-5. rc oscillator 7.6 x-tal oscillator the x-tal oscillator circuit is designed for use wi th an external crystal or ceramic resonator to provide an accurate clock source. in its typical configurati on, the x-tal oscillator is connected in a pierce oscillator configuration, as shown in figure 7-6 . this figure shows only the logical representat ion of the internal components and may not represent actual circui try. the oscillator conf iguration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) r ext c ext v dd mcu osc1 simoscen from sim stop_rclken config2 rc oscillator en see section 24. for component value requirements. bus clock from sim osc2 rcclk to clock selection mux
oscillator (osc) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 108 oscillator (osc) freescale semiconductor figure 7-6. crystal oscillator the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be r equired for all rang es of operation, especially with high frequency cryst als. refer to the crystal manufacturer?s data for more information. 7.7 i/o signals the following paragraphs describe the oscillator i/o signals. 7.7.1 crystal amplifi er input pin (osc1) osc1 pin is an input to the crystal o scillator amplifier or the input to the rc oscillator circuit. c 1 c 2 r b x 1 r s * *r s can be zero (shorted) when used with higher-frequency crystals. mcu refer to manufacturer?s data. osc2 osc1 see section 24. for component value requirements. simoscen from sim stop_xclken config2 xclk to clock selection mux
oscillator (osc) low power modes mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconduc tor oscillator (osc) 109 7.7.2 crystal amplifi er output pin (osc2) when the x-tal oscillator is selected, osc2 pin is the output of the crystal oscillator inverting amplifier. when the rc oscillator or internal osci llator is selected, osc2 pin is the output of the internal bus clock. 7.7.3 oscillator e nable signal (simoscen) the simoscen signal from the system integration module (sim) enables/disables the x-tal oscillator, the rc-oscilla tor, or the internal oscillator circuit. 7.7.4 cgm oscillat or clock (cgmxclk) the cgmxclk clock is output from the x-tal oscillator, rc oscillator or the internal oscillato r. this clock drives to cgm and other mcu sub- systems. 7.7.5 cgm refere nce clock (cgmrclk) this is buffered signal of cgmxclk, it is used by the cgm as the phase-locked-loop (pll) reference clock. 7.7.6 oscillator clock to time base module (oscclk) the oscclk is the referenc e clock that drives the timebase module. see section 12. timebase module (tbm) . 7.8 low power modes the wait and stop in structions put the mcu in low-power consumption standby modes.
oscillator (osc) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 110 oscillator (osc) freescale semiconductor 7.8.1 wait mode the wait instruction has no effect on the oscillator module. cgmxclk continues to drive to the clo ck generator module, and oscclk continues to drive the timebase module. 7.8.2 stop mode the stop instruction disables the x-tal or the rc oscillator circuit, and hence the cgmxclk clock stops running. for continuous x-tal or rc oscillator operation in stop mode, set the stop_ xclken (for x-tal) or stop_rclken (for rc) bit to logic 1 before entering stop mode. the internal oscillator clock conti nues operation in stop mode. it can be disabled by setting the stop_iclken bi t to logic 1 befor e entering stop mode. 7.9 oscillator during break mode the oscillator continues to drive cgmxclk when the de vice enters the break state.
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor clock generator module (cgm) 111 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 8. clock generator module (cgm) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 8.4.1 oscillator module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.4.2 phase-locked loop circ uit (pll) . . . . . . . . . . . . . . . . . . . 116 8.4.3 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.4.4 acquisition and tracking modes . . . . . . . . . . . . . . . . . . . . 118 8.4.5 manual and automati c pll bandwidth modes. . . . . . . . . . 118 8.4.6 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.4.7 special programming exceptions . . . . . . . . . . . . . . . . . . . 124 8.4.8 base clock selector ci rcuit . . . . . . . . . . . . . . . . . . . . . . . . 124 8.4.9 cgm external connectio ns . . . . . . . . . . . . . . . . . . . . . . . . 125 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.5.1 external filter capacitor pin (c gmxfc) . . . . . . . . . . . . . . 126 8.5.2 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . 126 8.5.3 pll anal og ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . 126 8.5.4 oscillator output frequency signal (cgmxc lk) . . . . . . . 126 8.5.5 cgm reference clock (cgmrclk) . . . . . . . . . . . . . . . . . 126 8.5.6 cgm vco clock output (cgmvclk) . . . . . . . . . . . . . . . . 127 8.5.7 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . . 127 8.5.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . 127 8.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.6.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.6.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . .130 8.6.3 pll multiplier select registers . . . . . . . . . . . . . . . . . . . . . 132 8.6.4 pll vco range select register . . . . . . . . . . . . . . . . . . . .133 8.6.5 pll reference divider select register . . . . . . . . . . . . . . . 134
clock generator module (cgm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 112 clock generator module (cgm) freescale semiconductor 8.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 8.8 special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 8.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 8.8.3 cgm during break inte rrupts. . . . . . . . . . . . . . . . . . . . . . . 136 8.9 acquisition/lock time spec ifications . . . . . . . . . . . . . . . . . . . 137 8.9.1 acquisition/lock time definitions. . . . . . . . . . . . . . . . . . . .137 8.9.2 parametric influences on reaction time . . . . . . . . . . . . . . 137 8.9.3 choosing a filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8.2 introduction this section describes the clock generator module (cgm). the cgm generates the base clock si gnal, cgmout, which is based on either the oscillator clock divi ded by two or the divi ded phase-locked loop (pll) clock, cgmpclk, divided by two. cgmout is th e clock from which the sim derives the system clocks, includi ng the bus clock, which is at a frequency of cgmout2. the pll clock, cgmvclk (an integer multiple of cgmpclk) provides clock reference for the pwm and analog modules. the pll is a frequency generator des igned for use with a low frequency crystal (typically 32.768khz) to generate a base frequency and dividing to a maximu m bus frequency of 8mhz.
clock generator module (cgm) features mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor clock generator module (cgm) 113 8.3 features features of the cgm include: phase-locked loop with output fr equency in integer multiples of an integer dividend of th e crystal reference low-frequency crystal operati on with low-power operation and high-output frequency resolution programmable prescaler for pow er-of-two increases in frequency programmable hardware voltage-c ontrolled oscillator (vco) for low-jitter operation automatic bandwidth control mode for low-jitt er operation automatic frequency lock detector cpu interrupt on entry or exit from locked condition configuration register bit to al low oscillator oper ation during stop mode 8.4 functional description the cgm consists of th ree major sub-modules: oscillator module ? the o scillator module generates the constant reference frequency clock, cgmrclk (buffered cgmxclk). phase-locked l oop (pll) ? the p ll generates the programmable vco frequency clock, cgmvclk, and the divided, cgmpclk. the cgmvclk provides the input reference clock to the pwm and analog modules. base clock selector circuit ? th is software-controlled circuit selects either cgmxcl k divided by two or the divided vco clock, cgmpclk, divided by two as t he base clock, cgmout. the sim derives the system clocks from either cgmout or cgmxclk. figure 8-1 shows the struct ure of the cgm. figure 8-2 is a summary of the cgm registers.
clock generator module (cgm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 114 clock generator module (cgm) freescale semiconductor figure 8-1. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator automatic mode control lock detector clock cgmxclk cgmout cgmvdv cgmvclk interrupt control cgmint cgmrdv pll analog 2 cgmrclk select circuit v dda cgmxfc v ssa lock auto acq vpr[1:0] pllie pllf mul[11:0] reference divider vrs[7:0] frequency divider pre[1:0] t0 adc, analog module phase-locked loop (pll) a b 1 s* *when s = 1, cgmout = b simdiv2 from sim to sim to sim rds[3:0] r cgmpclk simoscen oscillator (osc) module osc2 oscsel[1:0] oscclk[1:0] osc1 from sim iclk cgmrclk internal oscillator rc oscillator crystal oscillator mux see section 7. oscillator (osc) . n oscclk to timebase module (tbm) to pwm, to sim (and cop) analog module l 2 p 2 e
clock generator module (cgm) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor clock generator module (cgm) 115 addr.register name bit 7654321bit 0 $0036 pll control register (ptcl) read: pllie pllf pllon bcs pre1 pre0 vpr1 vpr0 write: reset:00100000 $0037 pll bandwidth control register (pbwc) read: auto lock acq 0000 r write: reset:0000000 $0038 pll multiplier select register high (pmsh) read: 0000 mul11 mul10 mul9 mul8 write: reset:00000000 $0039 pll multiplier select register low (pmsl) read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 $003a pll vco range select register (pmrs) read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 $003b pll reference divider select register (pmds) read: 0000 rds3 rds2 rds1 rds0 write: reset: 0 00 0 0001 = unimplemented r = reserved notes: 1. when auto = 0, pllie is forced clear and is read-only. 2. when auto = 0, pllf and lock read as clear. 3. when auto = 1, acq is read-only. 4. when pllon = 0 or vrs7:vrs0 = $0, bcs is forced clear and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. figure 8-2. cgm i/ o register summary
clock generator module (cgm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 116 clock generator module (cgm) freescale semiconductor 8.4.1 oscillator module the oscillator module provides two clock outputs cgmxclk and cgmrclk to the cgm module. cgmxcl k when selected, is driven to sim module to generate t he system bus clock. cg mrclk is used by the phase-lock-loop to provide a higher frequency system bus clock and the reference clock for the pwm and anal og modules. the oscillator module also provides the reference clock for the timebase module (tbm). see section 7. oscillator (osc) for detailed oscillator circuit description. see section 12. timebase module (tbm) for detailed description on tbm. see section 13. pulse wi dth modulator (pwm) for detailed description on pwm module. 8.4.2 phase-locked loop circuit (pll) the pll is a frequency gene rator that can operate in either acquisition mode or tracking mode, depending on the a ccuracy of the output frequency. the pll can change betw een acquisition and tracking modes either automat ically or manually. 8.4.3 pll circuits the pll consists of these circuits: voltage-controlled oscillator (vco) reference divider frequency pre-scaler modulo vco fr equency divider phase detector loop filter lock detector
clock generator module (cgm) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor clock generator module (cgm) 117 the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and cgmxfc noise. the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f vrs . modulating the voltage on the cg mxfc pin changes the frequency within this range. by design, f vrs is equal to the nom inal center-of-range frequency, f nom , (38.4 khz) times a linear fa ctor, l, and a power-of-two factor, e, or (l 2 e )f nom . cgmrclk is the pll reference clock, a buffered versio n of cgmxclk. cgmrclk runs at a frequency, f rclk , and is fed to t he pll through a programmable modulo referenc e divider, which divides f rclk by a factor, r. the di vider?s output is the final referenc e clock, cgmrdv, running at a frequency, f rdv =f rclk /r. with an external crystal (30khz?100khz), always set r = 1 for specified performance. with an external high-frequency clock source , use r to divi de the external frequency to between 30khz and 100khz. the vco?s output clock, cgmvcl k, running at a frequency, f vclk , is fed back through a programm able pre-scaler divider and a programmable modulo divider. the pre- scaler divides the vco clock by a power-of-two factor p (the cgmpclk) and the modulo divider reduces the vco clock by a fact or, n. the dividers? output is the vco feedback clock, cgmvdv, running at a frequency, f vdv =f vclk /(n 2 p ). (see 8.4.6 programming the pll for more information.) the phase detector then compares th e vco feedback clock, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase di fference between the two si gnals. the loop filter then slightly alters t he dc voltage on the external capacitor connected to cgmxfc based on the wi dth and direction of th e correction pulse. the filter can make fa st or slow correcti ons depending on its mode, described in 8.4.4 acquisiti on and tracking modes . the value of the external capacitor and the refer ence frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the freque ncies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to t he final reference frequency, f rdv . the circuit determines the mode of the pll and the lock condition based on this comparison.
clock generator module (cgm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 118 clock generator module (cgm) freescale semiconductor 8.4.4 acquisition and tracking modes the pll filter is manually or automatically conf igurable into one of two operating modes: acquisition mode ? in acquisition m ode, the filter can make large frequency corrections to the vco. this mode is used at pll start up or when the pll has suffered a severe noise hit and the vco frequency is far off the desired frequency. when in acquisition mode, the acq bit is clear in the pll bandwidth cont rol register. (see 8.6.2 pll bandwidth control register .) tracking mode ? in tracking mode , the filter makes only small corrections to the frequency of t he vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode wh en the vco frequency is nearly correct, such as when the pll is selected as the base clock source. (see 8.4.8 base clock se lector circuit .) the pll is automatically in tracking mode wh en not in acqui sition mode or when the acq bit is set. 8.4.5 manual and automa tic pll bandwidth modes the pll can change the bandwidth or oper ational mode of the loop filter manually or automatical ly. automatic mode is recommended for most users. in automatic bandwidth control mode (auto = 1), the lock detector automatically switches between acquisition and tracking modes. automatic bandwidth c ontrol mode also is us ed to determi ne when the vco clock, cgmvclk, is safe to us e as the source for the base clock, cgmout. (see 8.6.2 pll bandwidth control register .) if pll interrupts are enabled, th e software can wait for a pll interrupt request and then check the lock bit. if interrup ts are disabled, software can poll the lock bit cont inuously (during pll start-up, usually) or at periodic intervals. in either case, when the lo ck bit is set, the vco clock is safe to use as the source for the base clock. (see 8.4.8 base clock selector circuit .) if the vco is selected as th e source for the base clock and the lock bit is clear, the pll has suffered a seve re noise hit and the software must take appropriate ac tion, depending on the application. (see 8.7 interrupts for information and precautions on using interrupts.)
clock generator module (cgm) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor clock generator module (cgm) 119 the following conditions apply when t he pll is in automatic bandwidth control mode: the acq bit (see 8.6.2 pll bandwidth control register .) is a read-only indicator of the mode of the filter. (see 8.4.4 acquisition and tracking modes .) the acq bit is set when the vco fr equency is within a certain tolerance and is cleared when th e vco frequency is out of a certain tolerance. (see 8.9 acquisition/lock time specifications for more information.) the lock bit is a read-only indica tor of the locked state of the pll. the lock bit is set when the vco frequency is within a certain tolerance and is cleared when th e vco frequency is out of a certain tolerance. (see 8.9 acquisition/lock time specifications for more information.) cpu interrupts can occur if enabl ed (pllie = 1) when the pll?s lock condition changes, toggli ng the lock bit. (see 8.6.1 pll control register .) the pll also may operate in ma nual mode (auto = 0). manual mode is used by systems that do not requi re an indicator of the lock condition for proper operation. such syst ems typically operate well below f busmax .
clock generator module (cgm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 120 clock generator module (cgm) freescale semiconductor the following conditions appl y when in manual mode: acq is a writable control bit that controls t he mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. before entering tracking mode (acq = 1), software must wait a given time, t acq (see 8.9 acquisition/lock time specifications .), after turning on the pll by setting pllon in the pll control regi ster (pctl). software must wait a given time, t al , after entering tracking mode before selecting the pll as th e clock source to cgmout (bcs = 1). the lock bit is disabled. cpu interrupts from the cgm are disabled. 8.4.6 programming the pll the following procedure shows how to progr am the pll. note: the round function in t he following equations m eans that the real number should be round ed to the nearest integer number. 1. choose the desired bus frequency, f busdes , or the desired vco frequency, f vclkdes ; and then solve for the other. the relationship between f bus and f vclk is governed by the equation: where p is the power of two multip lier, and can be 0, 1, 2, or 3 2. choose a practical pll reference frequency, f rclk , and the reference clock divider, r. typica lly, the reference is 32.768khz and r = 1. frequency errors to the pll are corrected at a rate of f rclk /r. for stability and lock time reduction, this rate must be as fast as possible. the vco frequency must be an integer multiple of this rate. f vclk 2 p f cgmpclk 2 p 4 f bus ==
clock generator module (cgm) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor clock generator module (cgm) 121 the relationship between the vco frequency, f vclk , and the reference frequency, f rclk , is where n is the integer ran ge multiplier, between 1 and 4095. in cases where desired bus fr equency has some tolerance, choose f rclk to a value determined ei ther by other module requirements (such as modules wh ich are clocked by cgmxclk), cost requirements, or ideally, as high as the specified range allows. see section 24. electr ical specifications . choose the reference divider, r = 1. when the tolerance on the bus frequency is tight, choose f rclk to an integer divisor of f busdes , and r = 1. if f rclk cannot meet this requirement, use the following equation to solve for r with practical choices of f rclk , and choose the f rclk that gives the lowest r. 3. calculate n: 4. calculate and verify the adequacy of the vco and bus frequencies f vclk and f bus . f vclk 2 p n r ----------- f rclk () = r round r max f vclkdes f rclk -------------------------- ?? ?? ?? integer f vclkdes f rclk -------------------------- ?? ?? ?? ? ?? ?? ?? = n round rf vclkdes f rclk 2 p ------------------------------------ - ?? ?? ?? = f bus f vclk 2 p 4 ----------- = f vclk 2 p n r ----------- f rclk () =
clock generator module (cgm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 122 clock generator module (cgm) freescale semiconductor 5. select the vco?s powe r-of-two range multipli er e, according to this table: 6. select a vco linear ran ge multiplier, l, where f nom = 38.4khz 7. calculate and verify the ade quacy of the vco programmed center-of-range frequency, f vrs . the center-of-range frequency is the midpoint betwe en the minimum and maximum frequencies attainable by the pll. for proper operation, 8. verify the choice of p, r, n, e, and l by comparing f vclk to f vrs and f vclkdes . for proper operation, f vclk must be within the application?s tolerance of f vclkdes , and f vrs must be as close as possible to f vclk. note: exceeding the recommended ma ximum bus frequency or vco frequency can cr ash the mcu. frequency range e 0 < f vclk < 9,830,400 0 9,830,400 f vclk < 19,660,800 1 19,660,800 f vclk < 39,321,600 2 note: do not program e to a value of 3. l round f vclk 2 e f nom -------------------------- ?? ?? ?? = f vrs l2 e () f nom = f vrs f vclk ? f nom 2 e 2 --------------------------
clock generator module (cgm) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor clock generator module (cgm) 123 9. program the pll r egisters accordingly: a. in the pre bits of the pll control regi ster (pctl), program the binary equi valent of p. b. in the vpr bits of the pll control regi ster (pctl), program the binary equi valent of e. c. in the pll multiplier select register low (p msl) and the pll multiplier select register hi gh (pmsh), progr am the binary equivalent of n. d. in the pll vco range select register (pmrs), program the binary coded equivalent of l. e. in the pll referenc e divider select regi ster (pmds), program the binary coded eq uivalent of r. note: the values for p, e, n, l, and r can only be programmed when the pll is off (pllon = 0). table 8-1 provides numeric examples (numbers are in hexadecimal notation): table 8-1. numeric examples cgmvclk cgmpclk f bus f rclk rnpel 8.0 mhz 8.0 mhz 2.0 mhz 32.768 khz 1 f5 0 0 d1 9.8304 mhz 9.8304 mhz 2.4576 mhz 32.768 khz 1 12c 0 1 80 10.0 mhz 10.0 mhz 2.5 mhz 32.768 khz 1 132 0 1 83 16 mhz 16 mhz 4.0 mhz 32.768 khz 1 1e9 0 1 d1 19.6608 mhz 19.6608 mhz 4.9152 mhz 32.768 khz 1 258 0 2 80 20 mhz 20 mhz 5.0 mhz 32.768 khz 1 263 0 2 82 29.4912 mhz 29.4912 mhz 7.3728 mhz 32.768 khz 1 384 0 2 c0 32 mhz 32 mhz 8.0 mhz 32.768 khz 1 3d1 0 2 d0 32 mhz 16 mhz 4.0 mhz 32.768 khz 1 1e9 1 2 d0 32 mhz 8 mhz 2.0 mhz 32.768 khz 1 f5 2 2 d0 32 mhz 4 mhz 1.0 mhz 32.768 khz 1 7b 3 2 d0
clock generator module (cgm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 124 clock generator module (cgm) freescale semiconductor 8.4.7 special programming exceptions the programming method described in 8.4.6 programming the pll does not account for three possible exc eptions. a value of 0 for r, n, or l is meaningless when used in the eq uations given. to account for these exceptions: a 0 value for r or n is interpreted exactly the same as a value of 1. a 0 value for l disabl es the pll and prevents its selection as the source for the base clock. (see 8.4.8 base clock se lector circuit .) 8.4.8 base clock se lector circuit this circuit is used to select either the oscillator clock, cgmxclk, or the divided vco clock, cgmp clk, as the source of the base clock, cgmout. the two input clocks go thr ough a transition control circuit that waits up to three cgmxclk c ycles and three cgmpclk cycles to change from one clock so urce to the other. du ring this time, cgmout is held in stasis. the output of the transition contro l circuit is then divided by two to correct the duty cycle. therefore, the bus clock frequency, which is one-half of the base clock frequency , is one-fourth the frequency of the se lected clock (cgmxcl k or cgmpclk). the bcs bit in the pll cont rol register (pctl) sele cts which clock drives cgmout. the divided vco clock cannot be select ed as the base clock source if the pll is no t turned on. the pll cannot be turned off if the divided vco clock is selected. the pll cannot be turned on or off simultaneously with the selection or deselection of the divided vco clock. the divided vco clock also c annot be selected as the base clock source if the factor l is programmed to a 0. th is value would set up a condition inconsistent wi th the operation of the pll, so that the pll would be disabled and the o scillator clock would be forced as the source of the base clock.
clock generator module (cgm) i/o signals mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor clock generator module (cgm) 125 8.4.9 cgm exte rnal connections in its typical configurat ion, the cgm r equires up to four external components. figure 8-3 shows the external components for the pll: bypass capacitor, c byp filter network care should be taken with pcb routing in order to minimize signal cross talk and noise. (see 8.9 acquisition/lock ti me specifications for routing information, fi lter network and its effe cts on pll performance.) figure 8-3. cgm external connections 8.5 i/o signals the following paragraphs descr ibe the cgm i/o signals. c byp note: filter network in box can be replaced with a 0.47 f capacitor, but will degrade stability. 10 k ? 0.01 f 0.033 f 0.1 f v ssa v dda cgmxfc v dd mcu
clock generator module (cgm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 126 clock generator module (cgm) freescale semiconductor 8.5.1 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to fi lter out phase corrections. an external filter netw ork is connected to this pin. (see figure 8-3 .) note: to prevent noise problems, the filter network should be placed as close to the cgmxfc pin as po ssible, with minimum r outing distances and no routing of other sign als across the network. 8.5.2 pll analog power pin (v dda ) v dda is a power pin used by the analog portions of the p ll. connect the v dda pin to the same vo ltage potential as the v dd pin. note: route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 8.5.3 pll analog ground pin (v ssa ) v ssa is a ground pin used by the analog portions of the pll. connect the v ssa pin to the same volt age potential as the v ss pin. note: route v ssa carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 8.5.4 oscillator outp ut frequency signal (cgmxclk) cgmxclk is the osci llator output signal. it runs at the full speed of the oscillator, and is generated di rectly from the crystal oscillator circuit, the rc oscillator circuit, or the internal oscillator circuit. 8.5.5 cgm refere nce clock (cgmrclk) cgmrclk is a buffered version of cgmxclk, this clock is the reference clock for the phase-locked-loop circuit.
clock generator module (cgm) cgm registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor clock generator module (cgm) 127 8.5.6 cgm vco clock output (cgmvclk) cgmvclk is the clock out put from the vco. this clock can be used by the pulse width modulator (pwm ) module to gener ate high frequency pwm signals. this clock is also used by the analog module as a reference for signal sampling. 8.5.7 cgm base cl ock output (cgmout) cgmout is the clock output of the cgm. this signal goes to the sim, which generates the mcu clocks. cg mout is a 50 percent duty cycle clock running at twice the bus frequency. cgmout is software programmable to be eith er the oscillator outpu t, cgmxclk, divided by two or the divided vco clock, cgmpclk, divided by two. 8.5.8 cgm cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector. 8.6 cgm registers the following registers control and monitor operation of the cgm: pll control r egister (pctl) (see 8.6.1 pll control register .) pll bandwidth contro l register (pbwc) (see 8.6.2 pll bandwidth control register .) pll multiplier select registers (pmsh and pmsl) (see 8.6.3 pll multiplier select registers .) pll vco range select register (pmrs) (see 8.6.4 pll vco range select register .) pll reference di vider select register (pmds) (see 8.6.5 pll reference divider select register .)
clock generator module (cgm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 128 clock generator module (cgm) freescale semiconductor 8.6.1 pll control register the pll control register (pctl) contains the in terrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the vco power-of-two range selector bits. pllie ? pll interrupt enable bit this read/write bi t enables the pll to gener ate an interrupt request when the lock bit toggles, sett ing the pll flag, pllf. when the auto bit in the pll bandwidth c ontrol register (pbwc) is clear, pllie cannot be written and reads as logic 0. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ? pll interrupt flag bit this read-only bit is set wheneve r the lock bit toggles. pllf generates an interrupt request if th e pllie bit also is set. pllf always reads as logic 0 when t he auto bit in the pll bandwidth control register (pbwc) is clear . clear the pllf bi t by reading the pll control register. re set clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note: do not inadvertently cl ear the pllf bit. any re ad or read-modify-write operation on the pll control re gister clears the pllf bit. address: $0036 bit 7654321bit 0 read: pllie pllf pllon bcs pre1 pre0 vpr1 vpr0 write: reset:00100000 = unimplemented figure 8-4. pll cont rol register (pctl)
clock generator module (cgm) cgm registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor clock generator module (cgm) 129 pllon ? pll on bit this read/write bit activates t he pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving the base clock, cgmout (bcs = 1). (see 8.4.8 base clock selector circuit .) reset sets this bit so that the loop can stabi lize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit select s either the oscillator output, cgmxclk, or the divided vco clock, cgmpclk, as the sour ce of the cgm output, cgmout. cgmout frequency is one-half the fr equency of the selected clock. bcs cann ot be set while the p llon bit is clear. after toggling bcs, it may take up to three cgmxclk and three cgmpclk cycles to complete the tr ansition from one source clock to the other. during the transition, cgmout is held in stasis. (see 8.4.8 base clock sel ector circuit .) reset clears the bcs bit. 1 = cgmpclk divided by two drives cgmout 0 = cgmxclk divided by two drives cgmout note: pllon and bcs have built-in protec tion that prevents the base clock selector circuit from se lecting the vco clock as the source of the base clock if the pll is of f. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is clear. if the pll is off (pllon = 0), selecting cgmpclk require s two writes to the pll control register. (see 8.4.8 base clock se lector circuit .) pre1 and pre0 ? prescaler program bits these read/write bits control a pre scaler that selects the prescaler power-of-two mult iplier, p. (see 8.4.3 pll circuits and 8.4.6 programming the pll .) pre1 and pre0 cann ot be written when the pllon bit is set. reset clears these bits. these prescaler bits affects the re lationship between the vco clock and the final system bus clock.
clock generator module (cgm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 130 clock generator module (cgm) freescale semiconductor vpr1 and vpr0 ? vco power-o f-two range select bits these read/write bits control the vco?s hardware power-of-two range multiplier e that, in c onjunction with l (see 8.4.3 pll circuits , 8.4.6 programming the pll , and 8.6.4 pll vco range select register .) controls the hardware center-of-range frequency, f vrs . vpr1:vpr0 cannot be wr itten when the pllon bit is set. reset clears these bits. 8.6.2 pll bandwidth control register the pll bandwidth contro l register (pbwc): selects automatic or manual (software-controlled) bandwidth control mode indicates when the pll is locked in automatic bandwidth control mode , indicates when the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode table 8-2. pre1 and pre0 programming pre1 and pre0 p prescaler multiplier 00 0 1 01 1 2 10 2 4 11 3 8 table 8-3. vpr1 and vpr0 programming vpr1 and vpr0 e vco power-of-two range multiplier 00 0 1 01 1 2 10 2 4 note: do not program e to a value of 3.
clock generator module (cgm) cgm registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor clock generator module (cgm) 131 auto ? automatic bandwidth control bit this read/write bit sele cts automatic or manual bandwidth control. when initializing the p ll for manual operation (auto = 0), clear the acq bit before turning on the pll. reset cl ears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock, cgmvclk, is lo cked (running at the programmed frequency). when the auto bit is clear, lock reads as logic 0 and has no meaning. the writ e one function of this bit is reserved for test, so this bit must always be written a 0. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency inco rrect or unlocked acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tr acking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisiti on or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operati on is stored in a te mporary location and is recovered when manual oper ation resumes. rese t clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode address: $0037 bit 7654321bit 0 read: auto lock acq 0000 r write: reset:0000000 = unimplemented r= reserved figure 8-5. pll bandwidth control register (pbwcr)
clock generator module (cgm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 132 clock generator module (cgm) freescale semiconductor 8.6.3 pll multiplier select registers the pll multiplier select regist ers (pmsh and pmsl) contain the programming information for the modulo feedback divider. mul[11:0] ? multiplier select bits these read/write bits control the m odulo feedback divider that selects the vco frequency mu ltiplier n. (see 8.4.3 pll circuits and 8.4.6 programming the pll .) a value of $0000 in the multiplier select registers configure the modulo fee dback divider the same as a value of $0001. reset initializes the regi sters to $0040 for a default multiply value of 64. note: the multiplier select bits have built-in pr otection such that they cannot be written when the pll is on (pllon = 1). address: $0038 bit 7654321bit 0 read: 0 0 0 0 mul11 mul10 mul9 mul8 write: reset:00000000 = unimplemented figure 8-6. pll multiplier select register high (pmsh) address: $0039 bit 7654321bit 0 read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 figure 8-7. pll multiplier select regist er low (pmsl)
clock generator module (cgm) cgm registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor clock generator module (cgm) 133 8.6.4 pll vco r ange select register the pll vco range select register (pmrs) cont ains the programming information required fo r the hardware confi guration of the vco. vrs[7:0] ? vco r ange select bits these read/write bits control the hardware center-of-range linear multiplier l which, in conjunction with e (see 8.4.3 pll circuits , 8.4.6 programming the pll , and 8.6.1 pll control register .), controls the hardware ce nter-of-range frequency, f vrs . vrs[7:0] cannot be written when the pllon bi t in the pctl is set. (see 8.4.7 special programming exceptions .) a value of $00 in the vco range select regist er disables the pll and cl ears the bcs bit in the pll control register (pctl). (see 8.4.8 base clock selector circuit and 8.4.7 special programming exceptions .). reset initializes the register to $40 fo r a default range mult iply value of 64. note: the vco range select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1) and such that the vco clock cannot be selected as the source of the base cloc k (bcs = 1) if the vco range select bits are all clear. the pll vco range select register must be pr ogrammed correctly. incorrect programming can result in failure of the pll to achieve lock. address: $003a bit 7654321bit 0 read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 figure 8-8. pll vco range select register (pmrs)
clock generator module (cgm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 134 clock generator module (cgm) freescale semiconductor 8.6.5 pll reference divi der select register the pll reference divider select register (pmds) contains the programming information for t he modulo reference divider. rds[3:0] ? reference divider select bits these read/write bits control the modul o reference divider that selects the reference division factor, r. (see 8.4.3 pll circuits and 8.4.6 programming the pll .) rds[3:0] cannot be written when the pllon bit in the pctl is set. a va lue of $00 in the reference divider select register configur es the reference divider the same as a value of $01. (see 8.4.7 special progr amming exceptions .) reset initializes the register to $01 for a default divide value of 1. note: the reference divider select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1). note: the default divide value of 1 is recommended for all applications. address: $003b bit 7654321bit 0 read: 0 0 0 0 rds3 rds2 rds1 rds0 write: reset: 0 00 0 0001 = unimplemented figure 8-9. pll refe rence divider select register (pmds)
clock generator module (cgm) interrupts mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor clock generator module (cgm) 135 8.7 interrupts when the auto bit is set in the pll bandwidth control register (pbwc), the pll can generate a cpu interrupt request ev ery time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts ar e enabled or not. when the auto bit is clear, cpu interrupts from the p ll are disabled and pllf reads as logic 0. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit fr om lock. when the pll enters lock, the divided vco cl ock, cgmpclk, divided by two can be selected as the cgmo ut source by setting bcs in the pctl. when the pll exits lock, the vco clock frequency is corrupt , and appropriate precautions should be taken. if the a pplication is not fr equency sensitive, interrupts should be disabled to prev ent pll interrupt service routines from impeding software performance or from exceeding stack limitations. note: software can select the cgmpclk divided by two as the cgmout source even if the p ll is not locked (lock = 0). therefore, software should make sure the pll is lo cked before setting the bcs bit. 8.8 special modes the wait instruction pu ts the mcu in low pow er-consumption standby modes. 8.8.1 wait mode the wait instruction does not affect the cgm. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control r egister (pctl) to save power. less power-sensitive applications can dise ngage the pll wit hout turning it off, so that the pll cl ock is immediately availa ble at wait exit. this would be the case also when the pll is to wa ke the mcu from wait mode, such as when the pll is first enabled and wait ing for lock or lock is lost.
clock generator module (cgm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 136 clock generator module (cgm) freescale semiconductor 8.8.2 stop mode if the oscillator st op mode enable bit (sto p_iclken, stop_rclken, or stop_xclken in config2 register ) for the selected oscillator is configured to disabled t he oscillator in stop mode, then the stop instruction disables the cgm (oscillator and phase locked loop) and holds low all cgm outputs (cgm out, cgmvclk, cgmpclk, and cgmint). if the stop instruction is execut ed with the divided vco clock, cgmpclk, divided by two drivi ng cgmout, the pll automatically clears the bcs bit in the pll control register (p ctl), thereby selecting the oscillator clock, cgmxclk, di vided by two as the source of cgmout. when the mcu recovers from stop, the crystal clock divided by two drives cgmo ut and bcs remains clear. if the oscillator stop mode enable bit is conf igured for continuous oscillator operation in stop mode, t hen the phase locked loop is shut off but the cgmxclk will continue to drive the sim and other mcu sub- systems. 8.8.3 cgm during break interrupts the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during t he break state. (see 9.8.3 sim break flag control register .) to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect the pllf bit dur ing the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write the pll control register during the break state without affecting the pllf bit.
clock generator module (cgm) acquisition/lock time specifications mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor clock generator module (cgm) 137 8.9 acquisition/lock time specifications the acquisition and lo ck times of the pll are, in many applications, the most critical pll desi gn parameters. proper desig n and use of the pll ensures the highest stability and lowest acquisi tion/lock times. 8.9.1 acquisition/lock time definitions typical control systems refer to the ac quisition time or lock time as the reaction time, within specified tolera nces, of the system to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually specified as a percent of the step input or when the ou tput settles to the desi red value plus or minus a percent of the frequen cy change. therefore, t he reaction time is constant in this definit ion, regardless of the si ze of the step input. for example, consider a system with a 5 percent acqui sition time tolerance. if a command instruct s the system to change from 0hz to 1mhz, the acquisition time is the time ta ken for the frequency to reach 1mhz 50khz. 50khz = 5% of the 1mhz step input. if the system is operating at 1mhz and suffers a ?100kh z noise hit, the acquisition time is the time taken to re turn from 900khz to 1mhz 5khz. 5khz = 5% of the 100khz step input. other systems refer to ac quisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified toleranc es. therefore, the acquisition or lock time varies according to the original error in the output . minor errors may not even be registered. typical pll applications prefer to use this definition because the system requires the out put frequency to be within a certain tolerance of the desired fr equency regardless of the size of the initial error. 8.9.2 parametric in fluences on reaction time acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. these reaction times are not constant, however. many factors di rectly and indirect ly affect the acquisition time.
clock generator module (cgm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 138 clock generator module (cgm) freescale semiconductor the most critical parameter which af fects the reaction times of the pll is the reference frequency, f rdv . this frequency is the input to the phase detector and controls how often the pll makes corr ections. for stability, the corrections must be small compared to t he desired frequency, so several corrections are requir ed to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is under user control via the choice of crystal frequency f xclk and the r value programmed in the reference divider. (see 8.4.3 pll circuits , 8.4.6 programming the pll , and 8.6.5 pll reference divider select register .) another critical parameter is th e external filter network. the pll modifies the voltage on the vco by adding or subtracting charge from capacitors in this network. therefore, the rate at wh ich the voltage changes for a given frequency erro r (thus change in charge) is proportional to the capacitance. the size of the capacitor also is related to the stability of the pll. if the c apacitor is too sma ll, the pll cannot make small enough adjus tments to the volt age and the system cannot lock. if the capacitor is too large, the pll may not be able to adjust the voltage in a reasonable time. (see 8.9.3 choosing a filter .) also important is th e operating voltage po tential applied to v dda . the power supply potential alters the charac teristics of the p ll. a fixed value is best. variable supplies, such as bat teries, are acceptable if they vary within a known range at very slow speeds. noise on the power supply is not acceptable, because it caus es small frequency errors which continually change the acquisi tion time of the pll. temperature and processing also can af fect acquisition time because the electrical characteristics of the pll change. the part operates as specified as long as these influences stay within the specified limits. external factors, however, can caus e drastic changes in the operation of the pll. these factors include noise injected into t he pll through the filter capacitor, filter capacitor leakage, stray impedanc es on the circuit board, and even hum idity or circuit board contamination.
clock generator module (cgm) acquisition/lock time specifications mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor clock generator module (cgm) 139 8.9.3 choosing a filter as described in 8.9.2 parametric in fluences on re action time , the external filter network is critical to the stability and reaction time of the pll. the pll is also dependent on reference frequency and supply voltage. either of the filter networks in figure 8-10 is recommended when using a 32.768khz referenc e clock (cgmrclk). figure 8-10 (a) is used for applications requiring better stability. figure 8-10 (b) is used in low-cost applications where stabili ty is not critical. figure 8-10. pll filter 10 k ? 0.01 f 0.033 f v ssa 0.47 f v ssa (a) (b) cgmxfc cgmxfc
clock generator module (cgm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 140 clock generator module (cgm) freescale semiconductor
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor system integration module (sim) 141 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 9. system integration module (sim) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 144 9.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9.3.2 clock start-up from po r or lvi reset. . . . . . . . . . . . . . . . 145 9.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . 146 9.4 reset and system initiali zation. . . . . . . . . . . . . . . . . . . . . . . . 146 9.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 9.4.2 active resets from in ternal sources . . . . . . . . . . . . . . . . . 147 9.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 9.4.2.2 computer operati ng properly (cop) rese t. . . . . . . . . . 149 9.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . .150 9.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 150 9.4.2.6 monitor mode entry module rese t. . . . . . . . . . . . . . . . . 150 9.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . 151 9.5.2 sim counter during stop mode re covery . . . . . . . . . . . . . 151 9.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 151 9.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 9.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 9.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 9.6.1.3 interrupt status r egisters . . . . . . . . . . . . . . . . . . . . . . .155 9.6.1.4 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . 155 9.6.1.5 interrupt stat us register 2 . . . . . . . . . . . . . . . . . . . . . . . 157 9.6.1.6 interrupt stat us register 3 . . . . . . . . . . . . . . . . . . . . . . . 157 9.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 9.6.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
system integration module (sim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 142 system integration module (sim) freescale semiconductor 9.6.4 status flag protection in break mode . . . . . . . . . . . . . . . . 158 9.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 9.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 9.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 9.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 9.8.1 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 162 9.8.2 sim reset status regist er . . . . . . . . . . . . . . . . . . . . . . . . 163 9.8.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . 164 9.2 introduction this section describes the system integration module (sim). together with the cpu, the sim cont rols all mcu activities. a block diagram of the sim is shown in figure 9-1 . table 9-1 is a summary of the sim input/output (i/o) regist ers. the sim is a system state controller that coordinates cpu and exception ti ming. the sim is responsible for: bus clock generation and cont rol for cpu and peripherals: ? stop/wait/reset/bre ak entry and recovery ? internal clock control master reset control, includi ng power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture exp andable to 128 interrupt sources table 9-1 shows the internal signal names used in this section.
system integration module (sim) introduction mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor system integration module (sim) 143 figure 9-1. sim block diagram stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to cgm, osc) cgmout (from cgm) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock iclk (from osc) 2 v dd internal pullup device table 9-1. signal name conventions signal name description iclk internal oscillator clock cgmxclk selected oscillator clock from oscillator module cgmvclk, cgmpclk pll output and the divided pll output cgmout cgmpclk-based or oscillator-based clock output from cgm module (bus clock = cgmout 2) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal
system integration module (sim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 144 system integration module (sim) freescale semiconductor 9.3 sim bus clock control and generation the bus clock generator provides system clock signal s for the cpu and peripherals on the mcu. the syst em clocks are generated from an incoming clock, cg mout, as shown in figure 9-3 . this clock can come from either the oscillator modul e or from the on-chip pll. (see section 8. clock generator module (cgm) .) addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 note: writing a l ogic 0 clears sbsw. $fe01 sim reset status register (srsr) read: por pin cop ilop ilad 0 lvi 0 write: por:10000000 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) read: 00000if17if16if15 write:rrrrrrrr reset:00000000 = unimplemented r = reserved figure 9-2. sim i/o register summary
system integration module (sim) sim bus clock control and generation mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor system integration module (sim) 145 figure 9-3. cgm clock signals 9.3.1 bus timing in user mode, the inter nal bus frequency is either the oscillator output (cgmxclk) divided by four or the divided pll output (cgmpclk) divided by four. 9.3.2 clock start-up from por or lvi reset when the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripheral s are inactive and held in an inactive phase until after the 4096 iclk cycle por timeout has completed. the rst pin is driven low by the sim during this entire period. the ibus clocks start upon comp letion of the timeout. 2 bus clock generators system integration module monitor mode user mode simoscen oscillator (osc) module osc2 osc1 phase-locked loop (pll) cgmxclk cgmrclk it12 cgmout simdiv2 ptc1 to tim, adc stop mode clock to rest of mcu it23 to rest of mcu enable signals from config2 iclk to tbm oscclk cgmvclk to pwm sim counter
system integration module (sim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 146 system integration module (sim) freescale semiconductor 9.3.3 clocks in st op mode and wait mode upon exit from stop mode by an interr upt, break, or rese t, the sim allows iclk to clock the si m counter. the cpu and per ipheral clocks do not become active until af ter the stop delay tim eout. this timeout is selectable as 4096 or 32 iclk cycles. (see 9.7.2 stop mode .) in wait mode, t he cpu clocks are inactive. th e sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if t he module is active or i nactive in wait mode. some modules can be programmed to be active in wait mode. 9.4 reset and system initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating pr operly module (cop) low-voltage inhi bit module (lvi) illegal opcode illegal address all of these resets produce the vector $fffe :$ffff ($fefe:$feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to thei r default values and all modules to be returned to thei r reset states. an internal reset clear s the sim counter (see 9.5 sim counter ), but an external reset does not. each of th e resets sets a co rresponding bit in the sim reset status register ( srsr). (see 9.8 sim registers .)
system integration module (sim) reset and system initialization mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor system integration module (sim) 147 9.4.1 external pin reset the rst pin circuit includes an internal pull-up device. pulling the asynchronous rst pin low halts all processi ng. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 iclk cycles, assuming that neither the por nor the lvi was the source of the reset. see table 9-2 for details. figure 9-4 shows the relative timing. figure 9-4. extern al reset timing 9.4.2 active resets from internal sources all internal reset sour ces actively pull the rst pin low for 32 iclk cycles to allow resetting of ex ternal peripherals. the in ternal reset signal irst continues to be asserted for an additional 32 cycles (see figure 9-5). an internal reset can be caused by an illegal address, il legal opcode, cop timeout, lvi, or po r (see figure 9-6). note: for lvi or por resets , the sim cycles through 4096 + 32 iclk cycles during which the si m forces the rst pin low. the internal reset signal then follows the sequence fr om the falling edge of rst shown in figure 9-5 . table 9-2. pin bit set timing reset type number of cycles required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l iclk
system integration module (sim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 148 system integration module (sim) freescale semiconductor figure 9-5. inter nal reset timing the cop reset is asynchro nous to the bus clock. figure 9-6. sources of internal reset the active reset feature allows the par t to issue a reset to peripherals and other chips within a system built around the mcu. 9.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pul se to indicate that pow er-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 + 32 iclk cycles. thi rty-two iclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, thes e events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables cgmout. internal clocks to the cpu and m odules are held i nactive for 4096 iclk cycles to allow stabil ization of the oscillator. the rst pin is driven low during th e oscillator stabilization time. the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared. irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high iclk illegal address rst illegal opcode rst coprst lvi por internal reset
system integration module (sim) reset and system initialization mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor system integration module (sim) 149 figure 9-7. por recovery 9.4.2.2 computer operat ing properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all intern al reset sources. to prevent a cop module timeout, wr ite any value to location $ffff. writing to location $ffff clears th e cop counter and bits 12 through 5 of the sim counter. the s im counter output, which o ccurs at least every 2 13 ? 2 4 iclk cycles, drives the co p counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time befor e the first timeout. the cop module is disabled if the rst pin or the irq1 pin is held at v tst while the mcu is in monitor mode. the cop module can be disabled only through co mbinational logic c onditioned with the high voltage signal on the rst or the irq1 pin. this prevent s the cop from becoming disabled as a result of ex ternal noise. duri ng a break state, v tst on the rst pin disables the cop module. porrst osc1 iclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff irst
system integration module (sim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 150 system integration module (sim) freescale semiconductor 9.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bi t in the sim reset status register (srsr) and causes a reset. if the stop enable bit, st op, in the mask option regi ster is logic 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. 9.4.2.4 illegal address reset an opcode fetch from an unm apped address genera tes an illegal address reset. the sim ve rifies that t he cpu is fetching an opcode prior to asserting the ilad bit in the si m reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim acti vely pulls down the rst pin for all internal reset sources. 9.4.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit m odule (lvi) asserts its output to the sim when the v dd voltage falls to the lvi tripf voltage. the lvi bi t in the sim reset status register (srsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 4096 + 32 iclk cycles. thirty-two iclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 9.4.2.6 monitor m ode entry module reset the monitor mode entry modu le reset asserts its ou tput to the sim when monitor mode is entered in the condition where the reset vectors are blank ($ff). (see section 10. monitor rom (mon) .) when modrst gets asserted, an internal reset occu rs. the sim actively pulls down the rst pin for all inter nal reset sources.
system integration module (sim) sim counter mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor system integration module (sim) 151 9.5 sim counter the sim counter is used by the pow er-on reset module (por) and in stop mode recovery to allow the os cillator time to stabilize before enabling the internal bus (i bus) clocks. the sim c ounter also serves as a prescaler for the computer operati ng properly module (cop). the sim counter overflow supplies the cl ock for the cop module. the sim counter is 12 bits long and is clo cked by the falling edge of iclk. 9.5.1 sim counter during power-on reset the power-on reset module (por) dete cts power appli ed to the mcu. at power-on, the por ci rcuit asserts the signal porrst. once the sim is initialized, it enabl es the clock generation m odule (cgm) to drive the bus clock state machine. 9.5.2 sim counter du ring stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. af ter an interrupt, brea k, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the configuration register 1 (config1). if the ssrec bit is a logic 1, then the stop recovery is reduced from t he normal delay of 4096 iclk cycles down to 32 iclk cycles. this is i deal for applications using canned oscillators that do not require lo ng start-up times from stop mode. external crystal applicati ons should use the full st op recovery time, that is, with ssrec cleared. 9.5.3 sim counter and reset states external reset has no effect on the sim counter. ( see 9.7.2 stop mode for details.) the sim counter is free -running after all re set states. (see 9.4.2 active resets from internal sources for counter control and internal reset re covery sequences.)
system integration module (sim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 152 system integration module (sim) freescale semiconductor 9.6 exception control normal, sequential progra m execution can be chang ed in three different ways: interrupts: ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts 9.6.1 interrupts at the beginning of an interrupt, the cpu sa ves the cpu register contents on the sta ck and sets the interrupt ma sk (i bit) to prevent additional interrupts. at the end of an interrupt , the rti instruction recovers the cpu regist er contents from the stack so that normal processing can resume. figure 9-8 shows interrupt entry timing, and figure 9-9 shows interrupt recovery timing. figure 9-8. interrupt entry timing figure 9-9. interr upt recovery timing module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i-bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[15:8] pc ? 1[7:0] opcode operand i-bit
system integration module (sim) exception control mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor system integration module (sim) 153 interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which ve ctor to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serv iced (or the i bit is cleared). (see figure 9-10 .) figure 9-10. in terrupt processing no no no yes no no yes yes as many interrupts i bit set? from reset break i-bit set? irq1 interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers stack cpu registers set i-bit load pc with interrupt vector execute instruction yes yes as exist on chip interrupt?
system integration module (sim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 154 system integration module (sim) freescale semiconductor 9.6.1.1 hardwa re interrupts a hardware interrupt does not stop the current in struction. processing of a hardware interrupt begins after completion of t he current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts ar e not masked (i bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the sim proceeds with interrup t processing; other wise, the next instruction is fetched and executed. if more than one interrupt is pending at th e end of an instruction execution, the highest priority interrupt is serviced first. figure 9-11 demonstrates what hap pens when two interrupts are pending. if an interrupt is pending upon exit from the original inte rrupt service routine, the pending interrupt is serviced before the lda in struction is executed. figure 9-11 . interrupt recognition example the lda opcode is pr efetched by both th e int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during in terrupt entry. if the in terrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prio r to exiting the routine. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine
system integration module (sim) exception control mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor system integration module (sim) 155 9.6.1.2 swi instruction the swi instruction is a non-maskable instruct ion that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 9.6.1.3 interrupt status registers the flags in the interrupt status re gisters identify maskable interrupt sources. table 9-3 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. 9.6.1.4 interrupt status register 1 if6?if1 ? interrupt flags 6?1 these flags indicate the presence of interrupt r equests from the sources shown in table 9-3 . 1 = interrupt request present 0 = no interrupt request present bit 0 and bit 1 ? always read 0 address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 r=reserved figure 9-12. interrupt st atus register 1 (int1)
system integration module (sim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 156 system integration module (sim) freescale semiconductor table 9-3. interrupt sources priority int flag vector address interrupt source lowest if17 $ffda timebase module $ffdb if16 $ffdc analog module $ffdd if15 $ffde adc conversion complete $ffdf if14 $ffe0 keyboard $ffe1 if13 $ffe2 sci transmit $ffe3 if12 $ffe4 sci receive $ffe5 if11 $ffe6 sci error $ffe7 if10 $ffe8 mmiic $ffe9 if9 $ffea tim2 overflow $ffeb if8 $ffec tim2 channel 1 $ffed if7 $ffee tim2 channel 0 $ffef if6 $fff0 tim1 overflow $fff1 if5 $fff2 tim1 channel 1 $fff3 if4 $fff4 tim1 channel 0 $fff5 if3 $fff6 pll $fff7 if2 $fff8 irq2 $fff9 if1 $fffa irq1 $fffb $fffc swi $fffd $fffe reset highest $ffff
system integration module (sim) exception control mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor system integration module (sim) 157 9.6.1.5 interrupt status register 2 if14?if7 ? interr upt flags 14?7 these flags indicate the presence of interrupt r equests from the sources shown in table 9-3 . 1 = interrupt request present 0 = no interrupt request present 9.6.1.6 interrupt status register 3 if17?if15 ? interr upt flags 17?15 these flags indicate the presence of an interrupt request from the source shown in table 9-3 . 1 = interrupt request present 0 = no interrupt request present address: $fe05 bit 7654321bit 0 read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 r=reserved figure 9-13. interrupt st atus register 2 (int2) address: $fe06 bit 7654321bit 0 read: 00000if17if16if15 write:rrrrrrrr reset:00000000 r=reserved figure 9-14. interrupt st atus register 3 (int3)
system integration module (sim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 158 system integration module (sim) freescale semiconductor 9.6.2 reset all reset sources always have equal and highest pr iority and cannot be arbitrated. 9.6.3 break interrupts the break module can st op normal program flow at a software- programmable break point by assert ing its break interrupt output. (see section 23. break module (brk) .) the sim puts the cpu into the break state by forcing it to the swi vector loca tion. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 9.6.4 status flag pr otection in break mode the sim controls whether status fl ags contained in ot her modules can be cleared during break m ode. the user can sele ct whether flags are protected from being clea red by properly initiali zing the break clear flag enable bit (bcfe) in t he sim break flag contro l register (sbfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mo de without losing stat us flag information. setting the bcfe bit e nables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a 2- step clearing mechanism ? for example, a read of one register followed by the read or write of a nother ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal.
system integration module (sim) low-power modes mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor system integration module (sim) 159 9.7 low-power modes executing the wait or stop instruction puts t he mcu in a low power- consumption mode for st andby situations. the s im holds the cpu in a non-clocked state. the operation of ea ch of these modes is described in the following subsections. both stop and wait clear the interrupt mask (i) in the condition code regist er, allowing inte rrupts to occur. 9.7.1 wait mode in wait mode, t he cpu clocks are inactive while the peripheral clocks continue to run. figure 9-15 shows the timing fo r wait mode entry. a module that is active during wa it mode can wake up the cpu with an interrupt if the interrupt is enabled . stacking for the interrupt begins one cycle after the wait instruction duri ng which the interr upt occurred. in wait mode, the cpu clocks are i nactive. refer to the wait mode subsection of each module to see if th e module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode also can be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if t he cop disable bit, copd, in the mask option register is logic 0, then t he computer operat ing properly module (cop) is enabled and remains active in wait mode. figure 9-15. wait mode entry timing figure 9-16 and figure 9-17 show the timing for wait recovery. wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction.
system integration module (sim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 160 system integration module (sim) freescale semiconductor figure 9-16. wait recovery from interrupt or break figure 9-17. wait recover y from internal reset 9.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for inte rrupts begins after the selected stop recovery time has elapsed. reset or break al so causes an exit from stop mode. the sim disables the clock generator module output (cgm out) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ss rec bit in the confi guration register 1 (config1). if ssrec is set, stop recovery is r educed from the normal delay of 4096 iclk cycles down to 32. this is ideal for applications using canned oscillators that do not require long st art-up times from stop mode. note: external crystal applicati ons should use the full stop recovery time by clearing the ssrec bit. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 iclk 32 cycles 32 cycles
system integration module (sim) sim registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor system integration module (sim) 161 a break interrupt during stop mode sets the si m break stop/wait bit (sbsw) in the sim break st atus register (sbsr). the sim counter is held in reset from the execution of the stop instruction until th e beginning of stop recovery. it is then used to time the recovery period. figure 9-18 shows stop mode entry timing. note: to minimize stop current, all pins configured as i nputs should be driven to a logic 1 or logic 0. figure 9-18. stop mode entry timing figure 9-19. stop mode recovery from interrupt or break 9.8 sim registers the sim has three memory-mapped registers: sim break status r egister (sbsr) ? $fe00 sim reset status r egister (srsr) ? $fe01 sim break flag control r egister (sbfcr) ? $fe03 stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. iclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period
system integration module (sim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 162 system integration module (sim) freescale semiconductor 9.8.1 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from stop mode or wait mode. sbsw ? break wait bit this status bit is set w hen a break interrupt c auses an exit from wait mode or stop mode. clear sb sw by writing a logic 0 to it. reset clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break interrupt routine. the user can modify the return address on the st ack by subtractin g 1 from it. the following code is an example. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. r= reserved figure 9-20. sim break stat us register (sbsr) this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ lobyte equ if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register.
system integration module (sim) sim registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor system integration module (sim) 163 9.8.2 sim reset status register this register contains si x flags that show the s ource of the last reset provided all previous reset status bi ts have been cleared. clear the sim reset status register by reading it . a power-on reset se ts the por bit and clears all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operati ng properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address rese t bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ? low-voltage i nhibit reset bit 1 = last reset caused by the lvi circuit 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad 0 lvi 0 write: reset:10000000 = unimplemented figure 9-21. sim reset status register (srsr)
system integration module (sim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 164 system integration module (sim) freescale semiconductor 9.8.3 sim break flag control register the sim break control regist er contains a bit that enables software to clear status bits while t he mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear st atus bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 9-22. sim break flag c ontrol register (sbfcr)
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor monitor rom (mon) 165 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 10. monitor rom (mon) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 10.4.3 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 10.4.4 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 10.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 10.2 introduction this section describes the monitor rom (mon) and the monitor mode entry methods. the monitor rom allows complete testing of the mcu through a single-wir e interface with a host computer. monitor mode entry can be achieved without use of the higher test voltage, v tst , as long as vector addresses $fffe and $ffff are blank, thus reducing the hardware requirements fo r in-circuit programming.
monitor rom (mon) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 166 monitor rom (mon) freescale semiconductor 10.3 features features of the mo nitor rom include: normal user-mode pin functionality one pin dedicated to serial co mmunication between monitor rom and host computer standard mark/space non-return -to-zero (nrz) communication with host computer execution of code in ram or flash flash memory security feature 1 flash memory progr amming interface enhanced pll (phase-locke d loop) option to allo w use of external 32.768-khz crystal to generate in ternal frequency of 2.4576 mhz 368 bytes monitor rom code size ($fe10 to $ff7f) monitor mode entry wi thout high voltage, v tst , if reset vector is blank ($fffe and $ffff contain $ff) standard monitor mode entry if high voltage, v tst , is applied to irq1 10.4 functional description the monitor rom receives and exec utes commands from a host computer. figure 10-1 shows an example circui t used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute c ode downloaded into ram by a host computer while most mcu pins reta in normal operating mode functions. all communication between the host computer and t he mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and require s a pullup resistor. 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users.
monitor rom (mon) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor monitor rom (mon) 167 figure 10-1. moni tor mode circuit + + + mc145407 mc74hc125 rst irq1 cgmxfc osc1 osc2 v ss v dd pta0 v dd 10 k ? 0.1 f 10 k ? 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f ptc1 v dd b a (see note 1) 5 6 + v dd pta1 pta2 68hc908sr12 $ffff $fffe reset vectors v ssa v ssam v dda d c c c d d 6?30 pf 6?30 pf 32.768 khz xtal 10 m ? sw2 sw1 sw4 sw3 (see note 2) (see notes 2 (see note 2) (see note 3) notes: 1. for monitor mode entry when sw2 at position c (irq1 = v tst ): sw1: position a ? bus clock = cgmxclk 4 sw1: position b ? bus clock = cgmxclk 2 2. sw2, sw3, and sw4: position c ? enter moni tor mode using off-chip oscillator only. sw2, sw3, and sw4: position d ? enter monito r mode using 32.768khz xtal and internal pll. 3. see table 24-5 for irq1 voltage level requirements. 4. see table 10-1 for other monitor mode entry configurations. 10 k ? 0.01 f 0.033 f v tst 330 k ? and 3) v refl v refh 4.9152mhz/9.8304mhz
monitor rom (mon) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 168 monitor rom (mon) freescale semiconductor the monitor code allows enabling the pll to generate the internal clock, provided the reset vector is blank ($ff), when t he device is being clocked by a low-frequen cy crystal. this entry meth od, which is enabled when irq1 is held low out of reset, is inten ded to support serial communication/programm ing at 9600 baud in mo nitor mode by stepping up the external frequen cy (assumed to be 32.768 kh z) by a fixed amount to generate the desired inte rnal frequency (2.4576 mhz). if the reset vector is not blank (n ot $ff), the frequen cy stepping feature is not supported, because irq1 cannot be held low for monitor mode entry. with a non-blank reset vector , entry into monitor mode requires v tst on irq1 . 10.4.1 entering monitor mode table 10-1 shows the pin conditions fo r entering monitor mode. as specified in the table, monitor mode may be ente red after a por and will allow communication at 9600 baud pr ovided one of the fo llowing sets of conditions is met: 1. if $fffe and $ffff do not contain $ff (programmed state): ? the external clock is 4. 9152 mhz with pt c1 low or 9.8304 mhz with ptc1 high ?irq1 = v tst (pll off) 2. if $fffe and $ffff both contain $ff (erased state): ? the external clock is 9.8304 mhz ?irq1 = v dd (this can be implement ed through the internal irq1 pullup; pll off) 3. if $fffe and $ffff both contain $ff (erased state): ? the external clock is 32.768 khz (crystal) ?irq1 = v ss (this setting initiates the pll to boost the external 32.768 khz to an internal bus frequency of 2.4576 mhz)
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor monitor rom (mon) 169 monitor rom (mon) functional description table 10-1. monitor mode si gnal requirement s and options irq1 rst address $fffe/ $ffff pta2 pta1 pta0 (1) ptc1 external clock bus frequency pll cop baud rate comment xgndx xxxx x 0 xdisabled0no operation until reset goes high v tst v dd or v tst x 01104. 9152 mhz (2) 2.4576 mhz off disabled 9600 pta1 and pta2 voltages only required if irq1 = v tst ; ptc1 determines frequency divider v tst v dd or v tst x 01119. 8304 mhz (2) 2.4576 mhz off disabled 9600 pta1 and pta2 voltages only required if irq1 = v tst ; ptc1 determines frequency divider v dd v dd blank "$ffff" x x 1 x 9.8304 mhz (3) 2.4576 mhz off disabled 9600 external frequency always divided by 4 gnd v dd blank "$ffff" x x 1 x 32.768 khz (3) 2.4576 mhz on disabled 9600 pll enabled (bcs set) in monitor code v dd or gnd v tst blank "$ffff" xxxx x ? offenabled?enters user mode ? will encounter an illegal address reset v dd or gnd v dd or v tst not blankxxxx x ? offenabled?enters user mode notes : 1. pta0 = 1 if serial communication; pta0 = 0 if parallel communication (factory use only) 2. when irq1 = v tst , external clock must be derived by a 4.9152mhz or 9.8304mhz off-chip oscillator. 3. external clock is derived by a crystal or an off-chip oscillator.
monitor rom (mon) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 170 monitor rom (mon) freescale semiconductor if v tst is applied to irq1 and ptc1 is low upon monitor mode entry (above condition set 1), th e bus frequency is a divi de-by-two of the input clock. if ptc1 is high with v tst applied to irq1 upon monitor mode entry, the bus frequency will be a divide -by-four of the input clock. holding the ptc1 pin low when ent ering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if v tst is applied to irq1 . in this event, the cgmout freq uency is equal to the cgmxclk frequency, and the osc1 input directly generates internal bus clocks. in this case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. if entering monitor mode without high voltage on irq1 (above condition set 2 or 3, where appli ed voltage is either v dd or v ss ), then all port a pin requirements and conditi ons, including the pt c1 frequency divisor selection, are not in ef fect. this is to reduce circuit requirements when performing in-circuit programming. note: if the reset vector is blank and moni tor mode is entered, the chip will see an additional reset cycle after the init ial por reset. once the part has been programmed, the traditional method of applying a voltage, v tst , to irq1 must be used to enter monitor mode. the cop module is disabled in monitor mode bas ed on these conditions: if monitor mode was entered as a result of the reset vector being blank (above condition set 2 or 3), the cop is always disabled regardless of th e state of irq1 or rst . if monitor mode was entered with v tst on irq1 (condition set 1), then the cop is disabled as long as v tst is applied to either irq1 or rst . the second condition states that as long as v tst is maintained on the irq1 pin after entering mo nitor mode, or if v tst is applied to rst after the initial reset to get into monitor mode (when v tst was applied to irq1 ), then the cop will be disabled. in the latter situation, after v tst is applied to the rst pin, v tst can be removed from the irq1 pin in the interest of freeing the irq1 for normal functionality in monitor mode.
monitor rom (mon) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor monitor rom (mon) 171 figure 10-2 shows a simplified diagram of the moni tor mode entry when the reset vector is blank and just 1 x v dd voltage is applied to the irq1 pin. an external oscill ator of 9.8304 mhz is requi red for a baud rate of 9600, as the internal bus frequency is automatically set to the external frequency divided by four. figure 10-2. low-voltage moni tor mode entr y flowchart enter monitor mode with pin configuration shown in figure 10-1 by pulling rst low and then high. t he rising edge of rst latches monitor mode. once monitor mode is latched, the values on the specified pins can change. once out of reset, t he mcu waits for the host to send eight security bytes. (see 10.5 security .) after the security bytes, the mcu sends a break signal (10 cons ecutive logic 0s) to the hos t, indicating that it is ready to receive a command. in monitor mode, the mcu uses different ve ctors for reset, swi (software interrupt), and break interr upt than those fo r user mode. the alternate vectors are in the $f e page instead of the $ff page and allow code execution from the internal moni tor firmware instead of user code. is vector blank? por triggered? normal user mode monitor mode execute monitor code no no yes yes por reset
monitor rom (mon) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 172 monitor rom (mon) freescale semiconductor note: exiting monitor mode afte r it has been initiated by having a blank reset vector requires a power- on reset (por). pulling rst low will not exit monitor mode in this situation. table 10-2 summarizes the differences between user mode and monitor mode. 10.4.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. trans mit and receive baud rates must be identical. figure 10-3. moni tor data format 10.4.3 break signal a start bit (logic 0) foll owed by nine logic 0 bits is a break signal. when the monitor receives a break signal, it drives the pta0 pin high for the duration of two bits and t hen echoes back the break signal. figure 10-4. break transaction table 10-2. mode differences modes functions reset vector high reset vector low break vector high break vector low swi vector high swi vector low user $fffe $ffff $fffc $fffd $fffc $fffd monitor $fefe $feff $fefc $fefd $fefc $fefd bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit 2-stop bit delay before zero echo
monitor rom (mon) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor monitor rom (mon) 173 10.4.4 baud rate the communication baud rate is contro lled by the cryst al frequency and the state of the ptc1 pin (when irq1 is set to v tst ) upon entry into monitor mode. when ptc1 is high, the divide by ratio is 1024. if the ptc1 pin is at logic 0 upon entry into monitor m ode, the divide by ratio is 512. if monitor mode was entered with v dd on irq1 , then the divide by ratio is set at 1024, regardless of ptc1. if monitor mode was entered with v ss on irq , then the internal pll steps up the external fr equency, presumed to be 32.768 khz, to 2.4576 mhz. these latter two conditions for monitor mode entry require that t he reset vector is blank. table 10-3 lists external frequencies r equired to achieve a standard baud rate of 9600 bps. other standard baud rates can be accomplished using proportionally higher or lower frequency generators. if using a crystal as the clock source, be aware of the upper frequen cy limit that the internal clock module can handle. see 24.6 5.0v dc electrical characteristics and 24.8 5.0v control timing for this limit. 10.4.5 commands the monitor rom firmware uses these commands: read (read memory) write (write memory) iread (indexed read) table 10-3. monitor baud rate selection external frequency irq1 ptc1 internal frequency baud rate (bps) 4.9152 mhz v tst 0 2.4576 mhz 9600 9.8304 mhz v tst 1 2.4576 mhz 9600 9.8304 mhz v dd x 2.4576 mhz 9600 32.768 khz v ss x 2.4576 mhz 9600
monitor rom (mon) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 174 monitor rom (mon) freescale semiconductor iwrite (indexed write) readsp (read stack pointer) run (run user program) the monitor rom firmware echoes each received byte back to the pta0 pin for error checking. an 11-bit del ay at the end of each command allows the host to send a break c haracter to cancel the command. a delay of two bit times occurs bef ore each echo and before read, iread, or read sp data is returned. the dat a returned by a read command appears after the echo of t he last byte of the command. note: wait one bit ti me after each echo befor e sending the next byte. figure 10-5. read transaction figure 10-6. write transaction read read echo from host address high address high address low address low data return 13, 2 11 4 4 notes: 2 = data return delay, 2 bit times 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 44 1 = echo delay, 2 bit times write write echo from host address high address high address low address low data data notes: 2 = cancel command delay, 11 bit times 3 = wait 1 bit time before sending next byte. 11 3 11 3 3 32, 3 1 = echo delay, 2 bit times
monitor rom (mon) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor monitor rom (mon) 175 a brief description of each m onitor mode command is given in table 10-4 through table 10-9 . table 10-4. read (r ead memory) command description read byte from memory operand 2-byte address in high-byte:low-byte order data returned returns contents of specified address opcode $4a command sequence table 10-5. write (write memory) command description write byte to memory operand 2-byte address in high-byte:low-byte order; low byte followed by data byte data returned none opcode $49 command sequence read read echo sent to monitor address high address high address low data return address low write write echo from host address high address high address low address low data data
monitor rom (mon) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 176 monitor rom (mon) freescale semiconductor table 10-6. iread (i ndexed read) command description read next 2 bytes in memory from last address accessed operand 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence table 10-7. iwrite (i ndexed write) command description write to last address accessed + 1 operand single data byte data returned none opcode $19 command sequence iread iread echo from host data return data iwrite iwrite echo from host data data
monitor rom (mon) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor monitor rom (mon) 177 a sequence of iread or iwrite co mmands can access a block of memory sequentially over the full 64k-byte memory map. table 10-8. read sp (read stack pointer) command description reads stack pointer operand none data returned returns incremented stack pointer value (sp + 1) in high-byte:low- byte order opcode $0c command sequence table 10-9. run (run u ser program) command description executes pulh and rti instructions operand none data returned none opcode $28 command sequence readsp readsp echo from host sp return sp high low run run echo from host
monitor rom (mon) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 178 monitor rom (mon) freescale semiconductor the mcu executes the swi and pshh instructio ns when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instructions. before sendi ng the run command, the host can modify the stacked cpu registers to prepare to run the host program. the readsp command return s the incremented st ack pointer value, sp + 1. the high and low bytes of t he program counter are at addresses sp + 5 and sp + 6. figure 10-7. stack pointer at monitor mode entry 10.5 security a security feature discourages unaut horized reading of flash locations while in monitor mode. the host can bypass the securi ty feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locati ons $fff6?$fffd contain user- defined data. note: do not leave locati ons $fff6?$fffd blank . for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the power-on reset for the host to send th e eight security bytes on pi n pta0. if the received bytes match those at location s $fff6?$fffd, the hos t bypasses the security feature and can read al l flash locations and execute code from flash. security remains bypa ssed until a power-on reset occurs. if the reset was not a power-on reset, security remains bypassed and security code entry is not required. (see figure 10-8 .) condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7
monitor rom (mon) security mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor monitor rom (mon) 179 figure 10-8. monitor mode entry timing upon power-on reset, if the receiv ed bytes of the se curity code do not match the data at loca tions $fff6?$fffd, the host fails to bypass the security feature. the mcu remain s in monitor mode, but reading a flash location returns an invalid val ue and trying to exec ute code from flash causes an illegal address reset. after receiving the eight security bytes from the host, the mc u transmits a br eak character, signifying that it is ready to receive a command. note: the mcu does not transmit a break character unti l after the host sends the eight security bits. to determine whether the security c ode entered is correct, check to see if bit 6 of ram address $ 40 is set. if it is, then the correct security code has been entered and fl ash can be accessed. if the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to atte mpt another entry. after failing the security s equence, the flash modul e can also be mass erased by executing an erase routine that was downloaded into internal ram. the mass erase operat ion clears the security code locations so that all eight security bytes become $ff (blank). byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pta0 rst v dd 4096 + 32 iclk cycles 256 bus cycles (minimum) 1 4 1 1 2 1 break notes: 2 = data return delay, 2 bit times. 4 = wait 1 bit time before sending next byte. 4 from host from mcu 1 = echo delay, 2 bit times.
monitor rom (mon) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 180 monitor rom (mon) freescale semiconductor
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor timer interface module (tim) 181 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 11. timer interface module (tim) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 11.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 188 11.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .189 11.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 189 11.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 190 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 191 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 11.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.10.1 tim status and control register . . . . . . . . . . . . . . . . . . . . 196 11.10.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 11.10.3 tim counter modulo r egisters . . . . . . . . . . . . . . . . . . . . . 199 11.10.4 tim channel status and control registers . . . . . . . . . . . . 200 11.10.5 tim channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
timer interface module (tim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 182 timer interface module (tim) freescale semiconductor 11.2 introduction this section describes the timer in terface (tim) modul e. the tim is a two-channel timer that provides a timing refere nce with input capture, output compare, and pulse-wid th-modulation functions. figure 11-1 is a block diagram of the tim. this particular mcu has tw o timer interface modul es which are denoted as tim1 and tim2. 11.3 features features of the tim include: two input capture/ou tput compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse- width-modulation (pwm) signal generation programmable tim clock input with 7-frequency internal bus clock prescaler selection free-running or modul o up-count operation toggle any channel pin on overflow tim counter stop and reset bits
timer interface module (tim) pin name conventions mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor timer interface module (tim) 183 11.4 pin name conventions the text that follows describes bot h timers, tim1 and tim2. the tim input/output (i/o) pin names are t[1,2]ch0 (timer channel 0) and t[1,2]ch1 (timer channel 1) , where ?1? is used to indicate tim1 and ?2? is used to indicate tim2. the two tims share four i/o pins with four i/o port pins. the full names of t he tim i/o pins are listed in table 11-1 . the generic pin na mes appear in the text that follows. note: references to either timer 1 or time r 2 may be made in the following text by omitting the timer number. for ex ample, tch0 may refer generically to t1ch0 and t2ch0, and tch1 ma y refer to t1ch1 and t2ch1. 11.5 functional description figure 11-1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output co mpare functions. the tim counter modulo registers, tmodh:tmodl, contro l the modulo value of the tim counter. software can read th e tim counter value at any time without affecting the counting sequence. the two tim channels (per timer) are programm able independently as input capture or ou tput compare channels. table 11-1. pin name conventions tim generic pin names: t[1,2]ch0 t[1,2]ch1 full tim pin names: tim1 pta6/t1ch0 pta7/t1ch1 tim2 ptb4/t2ch0 ptb5/t2ch1
timer interface module (tim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 184 timer interface module (tim) freescale semiconductor figure 11-1. tim block diagram figure 11-2 summarizes the timer registers. note: references to either timer 1 or time r 2 may be made in the following text by omitting the timer number. for example, tsc may generically refer to both t1sc and t2sc. prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus bus clock ms1a t[1,2]ch0 t[1,2]ch1 interrupt logic port logic interrupt logic interrupt logic port logic
timer interface module (tim) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor timer interface module (tim) 185 addr.register name bit 7654321bit 0 $0020 timer 1 status and control register (t1sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 timer 1 counter register high (t1cnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0022 timer 1 counter register low (t1cntl) read: bit 7 654321bit 0 write: reset:00000000 $0023 timer 1 counter modulo register high (t1modh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0024 timer 1 counter modulo register low (t1modl) read: bit 7654321bit 0 write: reset:11111111 $0025 timer 1 channel 0 status and control register (t1sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 timer 1 channel 0 register high (t1ch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0027 timer 1 channel 0 register low (t1ch0l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0028 timer 1 channel 1 status and control register (t1sc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 11-2. tim i/o regist er summary (sheet 1 of 3)
timer interface module (tim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 186 timer interface module (tim) freescale semiconductor $0029 timer 1 channel 1 register high (t1ch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002a timer 1 channel 1 register low (t1ch1l) read: bit 7654321bit 0 write: reset: indeterminate after reset $002b timer 2 status and control register (t2sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $002c timer 2 counter register high (t2cnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $002d timer 2 counter register low (t2cntl) read: bit 7 654321bit 0 write: reset:00000000 $002e timer 2 counter modulo register high (t2modh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $002f timer 2 counter modulo register low (t2modl) read: bit 7654321bit 0 write: reset:11111111 $0030 timer 2 channel 0 status and control register (t2sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0031 timer 2 channel 0 register high (t2ch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 11-2. tim i/o regist er summary (sheet 2 of 3)
timer interface module (tim) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor timer interface module (tim) 187 11.5.1 tim counter prescaler the tim clock source can be one of the seven presca ler outputs. the prescaler generates seven clock rate s from the internal bus clock. the prescaler select bits, ps[2:0], in t he tim status and control register select the tim clock source. 11.5.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an acti ve edge occurs on the pin of an input capture channel, the tim latches the cont ents of the tim counter into the tim channel registers, tc hxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. $0032 timer 2 channel 0 register low (t2ch0l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0033 timer 2 channel 1 status and control register (t2sc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0034 timer 2 channel 1 register high (t2ch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0035 timer 2 channel 1 register low (t2ch1l) read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 11-2. tim i/o regist er summary (sheet 3 of 3)
timer interface module (tim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 188 timer interface module (tim) freescale semiconductor 11.5.3 output compare with the output compare function, the tim can gener ate a periodic pulse with a programmable polarity, duration, and fr equency. when the counter reaches the value in the r egisters of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. 11.5.3.1 unbuffer ed output compare any output compare channel can generate unbuffered output compare pulses as described in 11.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operati on for up to two counter overflow periods. for exampl e, writing a new value before the counter reaches the old value but after the c ounter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt rout ine to write a new, smaller output compare value may caus e the compare to be missed. the tim may pass the new value befor e it is written. use the following methods to synch ronize unbuffered changes in the output compare va lue on channel x: when changing to a smaller va lue, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse . the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare val ue, enable tim overflow interrupts a nd write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow perio d. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.
timer interface module (tim) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor timer interface module (tim) 189 11.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of the lin ked pair alternatel y control the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the output comp are value in the tim channel 0 registers initially controls the output on the tch0 pin. writing to the tim channel 1 registers enabl es the tim channel 1 registers to synchronously control t he output after the tim overflows. at each subsequent overflow, the tim channel regi sters (0 or 1) that control the output are the ones writte n to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note: in buffered output compare operati on, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 11.5.4 pulse widt h modulation (pwm) by using the toggle-on-overflow f eature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determi nes the period of th e pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between ov erflows is the period of the pwm signal. as figure 11-3 shows, the output compar e value in the tim channel registers determines t he pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on outpu t compare if the state of the pwm pulse is logic 1. program the tim to set the pi n if the state of the pwm pulse is logic 0.
timer interface module (tim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 190 timer interface module (tim) freescale semiconductor the value in the tim counter modu lo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is va riable in 256 in crements. writing $00ff (255) to the ti m counter modulo regi sters produces a pwm period of 256 times the in ternal bus clock period if the prescaler select value is $000. see 11.10.1 tim status and control register . figure 11-3. pwm peri od and pulse width the value in the tim chan nel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm sign al is variable in 256 increments. writing $008 0 (128) to the tim c hannel registers produces a duty cycle of 128 /256 or 50%. 11.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 11.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currentl y in the tim channel registers. an unsynchronized write to the ti m channel registers to change a pulse width value could cause incorrect oper ation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim overflow inte rrupt routine to write a new, smaller pulse width value may caus e the compare to be missed. the tim may pass the new value before it is written. tchx period pulse width overflow overflow overflow output compare output compare output compare
timer interface module (tim) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor timer interface module (tim) 191 use the following methods to synch ronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pu lse. the interrupt routi ne has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger val ue in an output compare interrupt routine (at the end of the current pulse) c ould cause two output compares to occur in the same pwm period. note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 11.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel re gisters of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writ ing to the tim channel 1 registers enables the ti m channel 1 registers to synchronously control the pulse width at t he beginning of the nex t pwm period. at each subsequent overflow, the tim channel regi sters (0 or 1) that control the pulse width are the ones written to last. tsc0 c ontrols and monitors the buffered pwm functi on, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a gener al-purpose i/o pin.
timer interface module (tim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 192 timer interface module (tim) freescale semiconductor note: in buffered pwm signal gener ation, do not write new pulse width values to the currently active channel registers. user so ftware should track the currently active channel to prevent writing a new value to the active channel. writing to the active c hannel registers is the same as generating unbuffer ed pwm signals. 11.5.4.3 pwm initialization to ensure correct operation when gen erating unbuffered or buffered pwm signals, use the follow ing initializat ion procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by se tting the tim stop bit, tstop. b. reset the tim counter and pre scaler by setting the tim reset bit, trst. 2. in the tim counter modulo regi sters (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (t chxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered outp ut compare or pwm signals) or 1:0 (for buffered output com pare or pwm si gnals) to the mode select bits, msxb:msxa. (see table 11-3 .) b. write 1 to the toggle- on-overflow bit, tovx. c. write 1:0 (to clear output on co mpare) or 1:1 (to set output on compare) to the edge/level se lect bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 11-3 .) note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control regist er (tsc), clear t he tim stop bit, tstop.
timer interface module (tim) interrupts mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor timer interface module (tim) 193 setting ms0b links chann els 0 and 1 and configur es them for buffered pwm operation. the tim channel 0 r egisters (tch0h:tch0l) initially control the buffered pwm output. tim status contro l register 0 (tscr0) controls and monitors the pwm signal from the linked channels. clearing the toggle-on-ove rflow bit, tovx, inhibi ts output toggles on tim overflows. subsequent outpu t compares try to forc e the output to a state it is already in and have no effect . the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. (see 11.10.4 tim channel status and c ontrol registers .) 11.6 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? th e tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overfl ow interrupt enable bit, toie, enables tim overflow cpu interr upt requests. tof and toie are in the tim status and control register. tim channel flags ( ch1f:ch0f) ? the chxf bi t is set when an input capture or output compar e occurs on channel x. channel x tim cpu interrupt requests ar e controlled by the channel x interrupt enable bit, chxie. c hannel x tim cpu interrupt requests are enabled when chxi e = 1. chxf and ch xie are in the tim channel x status and control register. 11.7 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes.
timer interface module (tim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 194 timer interface module (tim) freescale semiconductor 11.7.1 wait mode the tim remains active after the executi on of a wait instru ction. in wait mode, the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim befor e executing the wait instruction. 11.7.2 stop mode the tim is inactive after the executi on of a stop instru ction. the stop instruction does no t affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 11.8 tim during break interrupts a break interrupt st ops the tim counter. the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during t he break state. (see 9.8.3 sim break flag control register .) to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect status bits du ring the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write i/o registers during the break state wi thout affecting status bits. some status bits have a 2-st ep read/write clearing proced ure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit.
timer interface module (tim) i/o signals mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor timer interface module (tim) 195 11.9 i/o signals port a and port b each shares two of its pins with the tim. the four tim channel i/o pins are t1ch0, t1ch1 , t2ch0, and t2ch1 as described in 11.4 pin name conventions . each channel i/o pin is progr ammable independently as an input capture pin or an output compar e pin. t1ch0 and t2ch0 can be configured as buffered output compare or buffered pwm pins. 11.10 i/o registers note: references to either timer 1 or time r 2 may be made in the following text by omitting the timer number. for example, tsc may generically refer to both t1sc and t2sc. these i/o registers control and monitor operati on of the tim: tim status and control register (tsc) tim counter registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and con trol registers (tsc0, tsc1) tim channel registers (t ch0h:tch0l, tch1h:tch1l)
timer interface module (tim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 196 timer interface module (tim) freescale semiconductor 11.10.1 tim status and control register the tim status and control register (tsc): enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock tof ? tim overflow flag bit this read/write flag is set when t he tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register w hen tof is set and then writing a logic 0 to to f. if another tim overfl ow occurs before the clearing sequence is co mplete, then writing logic 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic 1 to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bi t enables tim overflow in terrupts when the tof bit becomes set. reset cl ears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled address: t1sc, $0020 and t2sc, $002b bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 11-4. tim st atus and control register (tsc)
timer interface module (tim) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor timer interface module (tim) 197 tstop ? tim stop bit this read/write bit stop s the tim counter. c ounting resumes when tstop is cleared. reset sets t he tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before enteri ng wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no ef fect on any other registers. counting resumes from $0000 . trst is cleared automatically after the tim counter is reset and always r eads as logic 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the tim counter as table 11-2 shows. reset clears the ps[2:0] bits. table 11-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 111 not available
timer interface module (tim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 198 timer interface module (tim) freescale semiconductor 11.10.2 tim count er registers the two read-only tim counter register s contain the high and low bytes of the value in the ti m counter. reading the high byte (tcnth) latches the contents of t he low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tc ntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latc hed during the break. address: t1cnth, $0021 and t2cnth, $002c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 = unimplemented figure 11-5. tim counter registers high (tcnth) address: t1cntl, $0022 and t2cntl, $002d bit 7654321bit 0 read: bit 7 654321bit 0 write: reset:00000000 = unimplemented figure 11-6. tim counte r registers low (tcntl)
timer interface module (tim) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor timer interface module (tim) 199 11.10.3 tim counter modulo registers the read/write tim modulo registers contain the modul o value for the tim counter. when the tim counter reaches t he modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow inte rrupts until the low byte (tmodl) is written. reset sets the ti m counter modulo registers. note: reset the tim counter bef ore writing to the tim counter modulo registers. address: t1modh, $0023 and t2modh, $002e bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 figure 11-7. tim counter mo dulo register high (tmodh) address: t1modl, $0024 and t2modl, $002f bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 11-8. tim counter m odulo register low (tmodl)
timer interface module (tim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 200 timer interface module (tim) freescale semiconductor 11.10.4 tim channel status and control registers each of the tim channel st atus and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or t oggling output on output compare selects rising edge, fall ing edge, or any edge as the active input capture trigger selects output toggl ing on tim overflow selects 0% and 1 00% pwm duty cycle selects buffered or unbuffer ed output compare/pwm operation address: t1sc0, $0025 and t2sc0, $0030 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 figure 11-9. tim channel 0 stat us and control register (tsc0) address: t1sc1, $0028 and t2sc1, $0033 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 figure 11-10. tim channel 1 stat us and control register (tsc1)
timer interface module (tim) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor timer interface module (tim) 201 chxf ? chann el x flag bit when channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matche s the value in the ti m channel x registers. when tim cpu interrupt requests ar e enabled (chxie = 1), clear chxf by reading tim channel x status and control register with chxf set and then writing a logic 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or out put compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x in terrupt enable bit this read/write bi t enables tim cpu interrupt service requests on channel x. reset clears the chxie bit. 1 = channel x cpu inte rrupt requests enabled 0 = channel x cpu interr upt requests disabled msxb ? mode select bit b this read/write bit sele cts buffered output co mpare/pwm operation. msxb exists only in the tim1 c hannel 0 and tim2 c hannel 0 status and control registers. setting ms0b disables the channel 1 status and control register and reverts tch1 to gen eral-purpose i/o. reset clears the msxb bit. 1 = buffered output com pare/pwm operation enabled 0 = buffered output compar e/pwm operation disabled msxa ? mode select bit a when elsxb:elsxa 0:0, this read/write bi t selects either input capture operation or unbuffered output compare/pwm operation. see table 11-3 . 1 = unbuffered output compare/pwm operation 0 = input capt ure operation
timer interface module (tim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 202 timer interface module (tim) freescale semiconductor when elsxb:elsxa = 0:0, this read/wr ite bit selects the initial output level of the tchx pin. see table 11-3 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bi ts in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an i nput capture channel, th ese read/write bits control the active edge- sensing logic on channel x. when channel x is an output co mpare channel, elsxb and elsxa control the channel x output beh avior when an output compare occurs. when elsxb and elsxa are both cl ear, channel x is not connected to an i/o port, and pin tchx is available as a general-purpose i/o pin. table 11-3 shows how elsxb and elsx a work. reset clears the elsxb and elsxa bits. table 11-3. mode, edge, and level selection msxb:msxa elsxb:elsxa mode configuration x0 00 output preset pin under port control; initial output level high x1 00 pin under port control; initial output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare
timer interface module (tim) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor timer interface module (tim) 203 note: before enabling a tim ch annel register for input capture operation, make sure that the tchx pin is st able for at leas t two bus clocks. tovx ? toggle on overflow bit when channel x is an output compar e channel, this read/write bit controls the behavior of the channel x output when t he tim counter overflows. when channel x is an i nput capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggle s on tim counter overflow 0 = channel x pin does not t oggle on tim counter overflow note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if bot h occur at the same time. chxmax ? channel x ma ximum duty cycle bit when the tovx bit is at logic 1, setting the chxmax bit forces the duty cycle of buffered and unbuffe red pwm signals to 100%. as figure 11-11 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 11-11. chxmax latency 11.10.5 tim c hannel registers these read/write registers contain the captured tim counter value of the input capture function or the outp ut compare value of the output compare function. the state of the tim channel register s after reset is unknown. output overflow tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare
timer interface module (tim) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 204 timer interface module (tim) freescale semiconductor in input capture mode (m sxb:msxa = 0:0), reading the high byte of the tim channel x registers (t chxh) inhibits input c aptures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x regist ers (tchxh) inhibits out put compares until the low byte (tchxl) is written. address: t1ch0h, $0026 and t2ch0h, $0031 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 11-12. tim channel 0 register high (tch0h) address: t1ch0l, $0027 and t2ch0l $0032 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 11-13. tim channel 0 register low (tch0l) address: t1ch1h, $0029 and t2ch1h, $0034 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 11-14. tim channel 1 register high (tch1h) address: t1ch1l, $002a and t2ch1l, $0035 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 11-15. tim channel 1 register low (tch1l)
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor timebase module (tbm) 205 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 12. timebase module (tbm) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 12.5 timebase register description. . . . . . . . . . . . . . . . . . . . . . . . 207 12.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 12.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 12.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 12.2 introduction this section describes the tim ebase module (tbm ). the tbm will generate periodic interrupts at user selectable rates using a counter clocked by the selected oscclk clock from the oscillator module. this tbm version uses 18 divi der stages, eight of whic h are user selectable. 12.3 features features of the tbm module include: software programmable 8s, 4s, 2s , 1s, 2ms, 1ms, 0.5ms, and 0.25ms periodic interrupt using 32.768-khz oscclk clock user selectable oscillator clo ck source enable duri ng stop mode to allow periodic wake-up from stop
timebase module (tbm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 206 timebase module (tbm) freescale semiconductor 12.4 functional description this module can generate a per iodic interrupt by divi ding the oscillator clock frequency, oscclk. the counter is initialized to all 0s when tbon bit is cleared. the counter, shown in figure 12-1 , starts counting when the tbon bit is set. when the counter overflows at the tap selected by tbr2:tbr0, the tbif bit gets set. if the tbie bit is set, an interrupt request is sent to the cpu . the tbif flag is cleared by writing a 1 to the tack bit. the first time the tbif flag is set after enabling the timebase module, the in terrupt is generated at approximately half of the overflow period. s ubsequent events occur at the exact period. the reference clock oscclk is derived from the os cillator module, see 7.3.2 tbm reference clock selection . figure 12-1. timebase block diagram (see section 7. oscillator (osc) .) 2 sel 0 0 0 0 0 1 0 1 0 0 1 1 tbif tbr1 tbr0 tbie tbon r tack tbr2 1 0 0 1 0 1 1 1 0 1 1 1 oscclk 2 2 2 2 2 2 2 2 2 2 2 2 2 8 16 32 64 2048 32768 65536 131072 tbmint 2 2 2 2 262144 from osc module
timebase module (tbm) timebase register description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor timebase module (tbm) 207 12.5 timebase register description the timebase has one regi ster, the tbcr, which is used to enable the timebase interrupts and set the rate. tbif ? timebase interrupt flag this read-only flag bit is set when the timebase counter has rolled over. 1 = timebase interrupt pending 0 = timebase interrupt not pending tbr2?tbr0 ? timebase rate selection these read/write bits are used to select the rate of timebase interrupts as shown in table 12-1 . address: $0046 bit 7654321bit 0 read: tbif tbr2 tbr1 tbr0 0 tbie tbon r write: tack reset:00000000 = unimplemented r = reserved figure 12-2. timebase cont rol register (tbcr) table 12-1. timebase rate sele ction for oscclk = 32.768 khz tbr2 tbr1 tbr0 divider timebase interrupt rate hz ms 0 0 0 262144 0.125 8000 0 0 1 131072 0.25 4000 0 1 0 65536 0.5 2000 0 1 1 32768 1 1000 100 64 512 ~2 101 32 1024 ~1 110 16 2048 ~0.5 1 1 1 8 4096 ~0.24
timebase module (tbm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 208 timebase module (tbm) freescale semiconductor note: do not change tbr2?t br0 bits while th e timebase is enabled (tbon = 1). tack ? timebase acknowledge the tack bit is a write-on ly bit and always reads as 0. writing a logic 1 to this bit clears tbif, the timebas e interrupt flag bit. writing a logic 0 to this bit has no effect. 1 = clear timebase interrupt flag 0 = no effect tbie ? timebase interrupt enabled this read/write bi t enables the timebase inte rrupt when the tbif bit becomes set. reset clears the tbie bit. 1 = timebase interrupt enabled 0 = timebase interrupt disabled tbon ? timebase enabled this read/write bit enables the timebase . timebase may be turned off to reduce power consumption when its function is not necessary. the counter can be initialize d by clearing and then se tting this bit. reset clears the tbon bit. 1 = timebase enabled 0 = timebase disabled and the counter initialized to 0s 12.6 interrupts the timebase module can interrupt the cpu on a regular basis with a rate defined by tbr 2?tbr0. when the timebase counter chain rolls over, the tbif flag is se t. if the tbie bit is set, enabling the timebase interrupt, the counter chain overflow will gene rate a cpu interrupt request. the interrupt ve ctor is defined in table 2-1 . vector addresses . interrupts must be acknowledged by writing a logic 1 to the tack bit.
timebase module (tbm) low-power modes mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor timebase module (tbm) 209 12.7 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. 12.7.1 wait mode the timebase module remains active after execution of the wait instruction. in wait m ode, the timebase r egister is not accessible by the cpu. if the timebase functions are not r equired during wait mode, reduce the power consumption by stopping the timebase before enabling the wait instruction. 12.7.2 stop mode the timebase module may remain acti ve after execution of the stop instruction if the osci llator has been enabled to operate during stop mode through the stop m ode oscillator enable bit (stop_iclken, stop_rclken, or stop_xclken) for the selected oscillator in the config2 register. the timebase modul e can be used in this mode to generate a periodic walk -up from stop mode. if the oscillator has not been enabled to operat e in stop mode, the timebase module will not be active during stop mode. in stop mode the timebase register is no t accessible by the cpu. if the timebase functions are not required during stop mode, reduce the power consumption by stopping the timebase before enabling the stop instruction.
timebase module (tbm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 210 timebase module (tbm) freescale semiconductor
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor pulse width modulator (pwm) 211 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 13. pulse width modulator (pwm) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 13.4 pwm period and resolution. . . . . . . . . . . . . . . . . . . . . . . . . . 214 13.5 pwm automatic phase cont rol . . . . . . . . . . . . . . . . . . . . . . .215 13.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 13.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 13.8 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 13.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 13.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 13.10.1 pwm control register (pwmcr) . . . . . . . . . . . . . . . . . . . 217 13.10.2 pwm clock control register (pwmccr) . . . . . . . . . . . . . 218 13.10.3 pwm data registers (pwmdr0 ?pwmdr2) . . . . . . . . . . 219 13.10.4 pwm phase control register . . . . . . . . . . . . . . . . . . . . . . 220 13.2 introduction this section describes the pulse width modula tor (pwm) module. the pwm module provides three 8-bi t pwm output c hannels, with an independent 8-bit counter for each channel. the pwm period is equal to seconds, where p clk is the pwm counter clock. for a 32mhz pwm counter cl ock, the pwm period is 8 s (a pwm frequency of 125khz). the automa tic phase control feature allows phase delays betwe en the channels. figure 13-2 shows the structur e of the pwm module. 256 1 p clk ---------------
pulse width modulator (pwm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 212 pulse width modulator (pwm) freescale semiconductor note: the cgm?s pll must be ru nning (enabled by setti ng pllon bit in the pll control register) if the cgmv clk is selected fo r the pwm module input clock. (see section 8. clock generator module (cgm) .) 13.3 features features of the pwm include the following: three independent pwm channels with independent counters pwm input clock select pwm input clock prescaler automatic phase control addr.register name bit 7654321bit 0 $0051 pwm control register (pwmcr) read: pwmen2 pwmen1 pwmen0 00 pch2 pch1 pch0 write: reset:00000000 $0052 pwm clock control register (pwmccr) read: pclksel 00000 pclk1 pclk0 write: reset:00000000 $0053 pwm data register 0 (pwmdr0) read: 0pwmd7 0pwmd6 0pwmd5 0pwmd4 0pwmd3 0pwmd2 0pwmd1 0pwmd0 write: reset:00000000 $0054 pwm data register 1 (pwmdr1) read: 1pwmd7 1pwmd6 1pwmd5 1pwmd4 1pwmd3 1pwmd2 1pwmd1 1pwmd0 write: reset:00000000 $0055 pwm data register 2 (pwmdr2) read: 2pwmd7 2pwmd6 2pwmd5 2pwmd4 2pwmd3 2pwmd2 2pwmd1 2pwmd0 write: reset:00000000 $0056 pwm phase control register (pwmpcr) read: phen phd6 phd5 phd4 phd3 phd2 phd1 phd0 write: reset:00000000 = unimplemented figure 13-1. pwm i/o register summary
pulse width modulator (pwm) features mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor pulse width modulator (pwm) 213 figure 13-2. pwm block diagram zero detector internal bus 8-bit pwm data register 8-bit data register buffer comparator 8-bit counter s r latch channel 0 to channel 1 to channel 2 pwmr0 q 8-bit counter 8-bit counter 2 2 2 mux pclk0 pclk1 pclksel cgmout cgmvclk a b 1 s p clk pwm0 when pclksel=0, pwmclk=cgmout. pwmclk b 1 a s pwm1 ptc1/pwm1 pin cdoen pch0 a b 1 s b 1 a s cdif ptc0/pwm0/cd pin to/from config2 from analog module pwmcr pwmccr pwmcr pch1 pwmcr to/from ptc1 ptc0 logic logic channel 1 output logic b 1 a s pwm2 ptc2/pwm2 pin pch2 pwmcr to/from ptc2 logic channel 2 output logic channel 0 output logic a is selected when s=0 a is selected when s=0 a is selected when s=0 from cgm if cgmvclk is selected, cgm?s pll must be running.
pulse width modulator (pwm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 214 pulse width modulator (pwm) freescale semiconductor 13.4 pwm period and resolution the pwm period is equal to , resolution is , where p clk is the pwm counter clock. the value in the pwm data register (pwmdr) defines th e period where the pwm output is high, the low period is equal to 256 minus that va lue. each pwm channel has its own counter and i/o control bits so it can be turned on and off independently. figure 13-3 shows the pwm output wave forms for a channel with different values in the pwm data register. figure 13-3. pwm output waveforms 256 1 p clk --------------- 1 p clk --------------- pwmdr = 256 pwm period = 256 t 128 t 128 t t t 255 t 255 t pwmdr = 1 pwmdr = 255 pwmdr = 128 t = 1 p clk note:
pulse width modulator (pwm) pwm automatic phase control mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor pulse width modulator (pwm) 215 13.5 pwm automatic phase control the automatic phase control function allows precise phase difference between the pwm output signals. figure 13-4 shows the phase delays bet ween the pwm output signals. figure 13-4. pwm auto matic phase control use the following steps to generat e phase difference on pwm channels: 1. clear pwm enable bits, pwmen[0:2], to logic 0. 2. write delay value in phd[0:6]. 3. set pwm automatic phase control enable bit, phen , to logic 1. 4. set the pwm channel enable bi ts, pch[0:2], to logic 1. 5. set the pwm enable bits, pwmen[ 0:2], to logic 1, to enable the pwm counters. when phase control is enabled, the pw m2 counter will start counting immediately, but the pwm1 and pw m0 counters will be held at zero. after the pwm2 counter reaches t he phase value, ph[0:6], the pwm1 counter is released and st arts counting. finally, when the pmw1 counter reaches the phase value, ph[0:6], pwm0 is released and starts counting. it is possible to change the value of ph[0:6] after the pwm1 counter has started and be fore the start of the pwm0 counter. this way, difference phases can be set bet ween pwm2 and pwm1; pwm1 and pwm0. pwm2 pwm1 pwm0 phase value 1 phase value 2 256 t 256 t 256 t 256 t
pulse width modulator (pwm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 216 pulse width modulator (pwm) freescale semiconductor the ph[0:6] value is used once to determine the start- up time of the different pwm counters. after t hat, all pwm count ers become free running counters and the phase between the co unters will remain unchanged. changing the va lue of ph[0:6] after all pwm counters are running has no effect. t he counters must first be disabled by clearing the pwm enable bits, pwmen[0:2], to logi c 0, before a new phase value is effective. automatic phase control is only av ailable with two (pwm2?pwm1) or three (pwm2?pwm0) pwm channels. 13.6 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. 13.7 wait mode the pwm module remains active af ter the execution of a wait instruction. in wait m ode, the pwm registers ar e not accessible by the cpu. if pwm functions are not required during wait mode, reduce power consumption by disabling the pw m before executing the wait instruction. 13.8 stop mode the pwm is inactive afte r the execution of a st op instruction. the stop instruction do es not affect register cond itions or the state of the pwm counters and output s. pwm operation re sumes when the mcu exits stop mode after an external interrupt.
pulse width modulator (pwm) i/o signals mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor pulse width modulator (pwm) 217 13.9 i/o signals the pwm module has three output pins shared with port c: ptc0/pwm0/cd, pwm1/ptc1, and ptc2 /pwm2. ptc0 is also shared with current flow detect output, cd, of the analog module, see (see 18.5 port c ). 13.10 i/o registers these i/o registers c ontrol pwm operation: pwm control r egister (pwmcr) pwm clock control register (pwmccr) pwm phase control register (pwmpcr) three pwm data regist ers (pwmdr0?pwmdr2) 13.10.1 pwm contro l register (pwmcr) the pwm control register (pwmcr ) enables/disables the independent pwm counters and port pins used for the pwm channels. pwmen2?pwmen0 ? pwm enable bits writing a 0 to the pwme nx bit clears the corresponding pwm counter and force the pwm channel x output to 0. rese t clears these bits. 1 = pwm channel x enabled 0 = pwm channel x is disabled; pwm counter cleared to zero and pwm channel x output forced to zero address: $0051 read: pwmen2 pwmen1 pwmen0 00 pch2 pch1 pch0 write: reset:00000000 = unimplemented figure 13-5. pwm cont rol register (pwmcr)
pulse width modulator (pwm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 218 pulse width modulator (pwm) freescale semiconductor pch2?pch0 ? pwm channel enable bits setting a bit will ena ble the corresponding po rt pin to be a pwm output pin. when a bit is set, the ddr bit has no ef fect on the port function. 1 = port pin is en abled for pwm output 0 = port pin is standard i/o pin exception for ptc0/pwm0/cd control: 13.10.2 pwm clock cont rol register (pwmccr) the pwm clock control register (p wmccr) selects an d defines the clock to the pwm counter, p clk . pclksel ? pwm input clock select bit this bit selects either the cgmout or cgmvclk clock as the input clock to the pwm counters. reset clears this bit. 1 = select cgmvclk as pwm input clock 0 = select cgmout (cpu bus clock) as pwm input clock table 13-1. ptc0 pin configuration pin cdoen bit ($001d) pch0 bit ($0051) pin function ptc0/pwm0/cd 00 ptc0 01 pwm0 1x cd address: $0052 read: pclksel 00000 pclk1 pclk0 write: reset:00000000 = unimplemented figure 13-6. pwm clock cont rol register (pwmccr)
pulse width modulator (pwm) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor pulse width modulator (pwm) 219 pclk1?pclk0 ? pwm clo ck prescaler bits these two bits select the divide ra tio used to divide the pwm input clock. table 13-2 shows the available clock divisions. 13.10.3 pwm data regi sters (pwmdr0?pwmdr2) the three pwm data registers (pwm dr0?pwmdr2) defi nes the high period for corresponding pwm channels. table 13-2. pwm counter cl ock prescaler selection pclk1 pclk0 pwm clock, p clk 0 0 source clock 1 0 1 source clock 2 1 0 source clock 4 1 1 source clock 8 address: $0053 read: 0pwmd7 0pwmd6 0pwmd5 0pwmd4 0pwmd3 0pwmd2 0pwmd1 0pwmd0 write: reset:00000000 figure 13-7. pwm data register 0 (pwmdr0) address: $0054 read: 1pwmd7 1pwmd6 1pwmd5 1pwmd4 1pwmd3 1pwmd2 1pwmd1 1pwmd0 write: reset:00000000 figure 13-8. pwm data register 1 (pwmdr1) address: $0055 read: 2pwmd7 2pwmd6 2pwmd5 2pwmd4 2pwmd3 2pwmd2 2pwmd1 2pwmd0 write: reset:00000000 figure 13-9. pwm data register 2 (pwmdr2)
pulse width modulator (pwm) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 220 pulse width modulator (pwm) freescale semiconductor the value of each pwm data register is continuously com pared with the content of a pwm count er to determine the st ate of each pwm channel output pin. a value of $00 l oaded into these regi ster results in a continuously low output on the corresponding pwm output pi n. a value of $80 results in a 50% duty cycle output and so on. the maximum value, $ff correspond to an output which is a "1 " for 255/256 of the pwm cycle. a new value written to th e pwm data register will not be effective until the end of the cu rrent pwm period. upon the end of the current pwm period, the contain of th e pwm data register is l oaded into the pwm data buffer, the value of t he pwm data buffer cont rols the pwm output. 13.10.4 pwm phase control register the pwm phase control register (pwmpcr) enables the automatic phase control and sets the phase values between the pwm channels. phen ? pwm automatic phase control enable bit setting this bit to 1 will enable the automatic phase co ntrol function. reset clears this bit. 1 = automatic phase control enabled 0 = automatic phase control disabled phd6?phd0 ? pwm phase value bits this 7-bit phase va lue is used to determined t he start-up time of the different pwm counters when phen bit is set. reset clea rs these bits. address: $0056 read: phen phd6 phd5 phd4 phd3 phd2 phd1 phd0 write: reset:00000000 figure 13-10. pwm phase co ntrol register (pwmpcr)
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor analog module 221 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 14. analog module 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 14.4.1 on-chip temperature sensor . . . . . . . . . . . . . . . . . . . . . . 223 14.4.2 two-stage amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 14.4.3 amplifier response time . . . . . . . . . . . . . . . . . . . . . . . . . . 224 14.4.4 current flow detecti on amplifier . . . . . . . . . . . . . . . . . . . . 225 14.4.5 current flow detect ou tput . . . . . . . . . . . . . . . . . . . . . . . . 225 14.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 14.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 14.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 14.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 14.7 analog module i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . 226 14.7.1 analog module control register (amcr) . . . . . . . . . . . . . 226 14.7.2 analog module gain control r egister (amgcr) . . . . . . . . 227 14.7.3 analog module status and co ntrol register (amscr) . . . 228 14.2 introduction this section describes the analog module. the analog module is designed to be use in conjunction wi th the analog-to-digital converter module for monitoring te mperature, charge and di scharge currents in smart battery applications. note: the analog module uses clo ck signals from the cg m?s pll, therefore the pll must be running ? pllon bit in the pll control register must be set. (see section 8. clock g enerator module (cgm) .)
analog module data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 222 analog module freescale semiconductor 14.3 features the features of the analog module include the following: temperature sensor current flow det ection amplifier two-stage amplifier figure 14-1. analog module block diagram 0.01 ? r sense i sense opout external batt + batt ? thermistor in0 in1 in2 in3 tsout opin2/ atd1 opin1/ atd0 v ssam 2-stage amp clock divider adciclk ? + internal reference analog module interrupt request dq r v dd ? + v det ?9mv ptc0 logic ptc0/ pwm0/ cd from config2 cgmxclk gaina[3:0] gainb[3:0] do[2:0] opif cdif v ssa internal temperature sensor atd1 to adc to adc batt + batt ? to irq logic dof opifr amien cdifr cdoen opch[1:0] amcdiv[1:0] cdif opif atd0 from adc analog module amclk cgmvclk from cgm
analog module functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor analog module 223 14.4 functional description figure 14-1 shows the block diagram of the analog module. the central component of the analog module is the two-stage gain amplifier used for amplifying the small signals on the analog input pins, opin1 and opin2. these two signals feed into a multiple xer together with the signal from the internal temperatur e sensor and a reference input. the selected signal is then fed into the two-stage gain amplifie r before going into the analog-to-digital converter (adc ) as opout. the opin1 and opin2 pins can also feed directly into the adc as channels atd0 and atd1 respectively, without any amplification. 14.4.1 on-chip temperature sensor the on-chip temperature sensor is designed to measure temperatures from ?20 c to 70 c. the output of the inter nal temperature sensor tsout is amplified by the two- stage amplifier. the amplified temperature sensor signal is routed to the analog-t o-digital converter for analog-to-digital conversion (see figure 14-1 ). addr.register name bit 7654321bit 0 $000e analog module control register (amcr) read: pwr1 pwr0 opch1 opch0 amien do2 do1 do0 write: reset:00000000 $000f analog module gain control register (amgcr) read: gainb3 gainb2 gainb1 gainb0 gaina3 gaina2 gaina1 gaina0 write: reset:00000000 $0010 analog module status and control register (amscr) read: amcdiv1 amcdiv0 0 opif 0 dof 0 cdif write: opifr cdifr reset:00u000u0 = unimplemented u = unaffected figure 14-2. analog modul e i/o register summary
analog module data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 224 analog module freescale semiconductor 14.4.2 two-stage amplifier the two-stage amplifier is used to am plify small input signals from the on-chip temperature sensor or exter nal voltage sources such as external thermistor and current sensing resi stor, for temperature and current monitoring. the am plified signal, opout, is f ed to the adc module for analog-to-digital conversi on. the gain of the tw o-stage amplifier is defined by the gainax and gainbx bits in the analog module gain control register (amgcr) (see figure 14-1 ). 14.4.3 amplifier response time the two-stage amplifier requires t he input signal to be stable for sampling. this signal hold- time varies with gain se tting for stage-1 of the two-stage amplifier, and is determined by the formula: 10 + [(gain of stage- 1 amplifier ? 1) 2] amclk cycles the amclk clock is the analog amplifier clock, which is divided from the adc clock, adciclk. the time for the two-sta ge amplifier to amplify the input signal to the desired output is dependent on the gain sett ing in both stag es of the two- stage amplifier. the amp lifier response time is determined by the formula: 70 + (8 gain of stage-1) + (6 gain of stage-2) amclk cycles this amplifier response time should be added to the adc conversion time to obtain the total time for the small-signal conversion. therefore, conversion time for opinx signals, wi th amplification is: amplifier response time + adc conversion time
analog module interrupts mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor analog module 225 14.4.4 current flow detection amplifier the current flow detecti on amplifier is used to detect charge and discharge current flowing through an external sensing resistor, r sense . the current flow detection flag cdif is set wh en the voltage at opin1 exceeds ?9mv (typical ) (0.9 ampere when r sense = 0.01 ? ). when set, cdif can generate an interrupt re quest to the cpu when the analog module interrupt enable bi t amien is set (see figure 14-1 ). 14.4.5 current flow detect output the current detect flag, cd if, can be configured fo r direct control to other external circuitry. when the cdoen bit in conf ig2 is set, the status of cdif is reflected on the ptc0/pwm0/cd pin. (see 5.5 configuration regi ster 2 (config2) and 18.5 port c .) 14.5 interrupts when the amien bit is set, the analog module is capable of generating cpu interrupt requests. the inte rrupt vector is defined in table 2-1 . vector addresses . 14.6 low-power modes the stop and wait instructions put the mcu in low power- consumption standby modes. 14.6.1 wait mode in wait mode the analog module if enabled, continues to operate and may generate an interrupt to trigger the m cu out of wait mode. 14.6.2 stop mode in stop mode, the temperature sens or and the two-stag e amplifier are disabled, but the current flow detection amplifie r (when enabled) continues to operate if the oscillator is enabled in stop mode. when amien is set, cdif can be used to wake-up the mcu from the stop mode.
analog module data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 226 analog module freescale semiconductor 14.7 analog module i/o registers three registers control and monitor the operation of the analog module: analog module control register (amcr) ? $000e analog module gain contro l register (amgcr) ? $000f analog module status and cont rol register (amscr) ? $0010 14.7.1 analog module c ontrol register (amcr) the analog module control register (amcr): powers on and off analog sub-modules selects the input signal to the two-st age amplifier enables analog modul e interrupt requests offset adjustment for calibration pwr1?pwr0 ? analog modul e power control bits these read/write bits power on/off t he different functions within the analog module. reset clears the pwr1 and pwr0 bits. address: $000e bit 7654321bit 0 read: pwr1 pwr0 opch1 opch0 amien do2 do1 do0 write: reset:00000000 figure 14-3. analog module control register (amcr) table 14-1. analog module power control pwr1 pwr0 current detect module temperature sensor two-stage amplifier 00 off off off 01 on off off 10 off off on 1 1 on on on
analog module analog module i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor analog module 227 opch1?opch0 ? amplifier c hannel select control bits these read/write bits select the inpu t source to be amplified by the two-stage amplifier. reset clea rs the opch1 and opch0 bits. amien ? analog modul e interrupt enable setting this bit will enab le the cdif and opif flags to generate an cpu interrupt requests. re set clears the amien bit. 1 = analog module cpu in terrupt requests enabled 0 = analog module cpu in terrupt requests disabled do[2:0] ? dc offset control bits set these bits to zero for opt imum analog module performance. 14.7.2 analog module gain control register (amgcr) the analog module gain control register (amgcr) select s the two gains for the two-stage amplifier. table 14-2. amplifier c hannel select control bits opch1 opch0 input source comments 00 v ssam external negative reference 0 1 opin1/atd0 external pin 1 0 opin2/atd1 external pin 1 1 tsout (internal) internal temperature sensor address: $000f bit 7654321bit 0 read: gainb3 gainb2 gainb1 gainb0 gaina3 gaina2 gaina1 gaina0 write: reset:00000000 figure 14-4. analog module gain control register (amgcr)
analog module data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 228 analog module freescale semiconductor gainb[3:0] ? analog module 2nd-stage gain control bits these read/write bits define the 2nd-stage gain of the two-stage amplifier. the ov erall gain of the amplifier equals the 1st-stage gain multiplied by the 2nd-stag e gain. reset clears the gainb[3:0] bits. gaina[3:0] ? analog module 1st-stage gain control bits these read/write bits define the 1st-stage gain of the two-stage amplifier. the ov erall gain of the amplifier equals the 1st-stage gain multiplied by the 2nd-stag e gain. reset clears the gaina[3:0] bits. 14.7.3 analog module status and control r egister (amscr) the analog module status and control r egister (amscr): selects input clock divider value monitors and clears the ampl ifier ready interrupt flag monitors dc offset flag monitors and clears the current detect interrupt flag table 14-3. analog module gain values gainx3 gainx2 gainx1 gainx0 amplifier gain 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16
analog module analog module i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor analog module 229 amcdiv[1:0] ? anal og module clock divider control bits these read/write bits select the analog module input clock divider value. the adc clock, adiclk, is di vided by this value to obtain the amclk. reset clears t he amcdiv[1:0] bits. set amcdiv1 and amcdiv0 bits to zero for optimum analog module performance. opifr ? amplifier read y interrupt flag reset writing a logic 1 to th is write-only bit clear s the opif bit. opifr always reads as a logic 0. reset does not affect opifr. 1 = clear opif bit 0 = no affect on opif bit opif ? amplifier r eady interrupt flag this read-only bit is se t when the output of the two-stage amplifier is ready. a cpu interrupt r equest will be generated if the amien bit is also set. reset clears opif bit. 1 = two-stage amplifier output is ready 0 = two-stage amplifier output is not ready address: $0010 bit 7654321bit 0 read: amcdiv1 amcdiv0 0 opif 0 dof 0 cdif write: opifr cdifr reset:00u000u0 = unimplemented u = unaffected figure 14-5. analog module status and contro l register (amscr) table 14-4. analog modul e clock divider select amcdiv1 amcdiv0 divider value 00 2 01 4 10 8 11 16
analog module data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 230 analog module freescale semiconductor dof ? dc offset flag this is a reserved bit. cdifr ? current detect interrupt flag reset writing a logic 1 to th is write-only bit clear s the cdif bit. cdifr always reads as a logic 0. reset does not affect cdifr. 1 = clear cdif bit 0 = no affect on cdif bit cdif ? current detect interrupt flag this read-only bit is set when the voltage devel oped across the sense resistor, r sense is equal to or greater than v det (the current sense amplifier comparator trip voltage, ty pically ?9mv). cdif generates an cpu interrupt request if amien bit is also set. the cdif bit is cleared by writing a logic 1 to the cd ifr bit. reset clears cdif bit. 1 = current detect interrupt has occurred 0 = no current detect interr upt since cdif last cleared
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor analog-to-digital converter (adc) 231 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 15. analog-to-digital converter (adc) 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 15.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 15.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 15.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 15.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.4.5 auto-scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.4.6 result justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 15.4.7 data register interlocki ng . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.4.8 monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 15.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 15.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 15.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.7.1 adc voltage in (v adin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.7.2 adc analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . 240 15.7.3 adc analog ground pin (v ssa ). . . . . . . . . . . . . . . . . . . . . 240 15.7.4 adc voltage reference high pin (v refh ). . . . . . . . . . . . . 241 15.7.5 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . 241 15.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 15.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . .242 15.8.2 adc clock control regi ster. . . . . . . . . . . . . . . . . . . . . . . . 244 15.8.3 adc data register 0 (adrh0 and a drl0). . . . . . . . . . . . 246 15.8.4 adc auto-scan mode data registers (adrl1?adrl3). . 248 15.8.5 adc auto-scan control register (adascr). . . . . . . . . . . 248
analog-to-digital converter (adc) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 232 analog-to-digital converter (adc) freescale semiconductor 15.2 introduction this section describes the analog-to-digital converter (adc). the adc is a 14-channel 10-bit linear successive approximation adc. 15.3 features features of the ad c module include: fourteen channel s with multiplexed input high impedance buffered input linear successive approximation with monotonicity 10-bit resolution single or cont inuous conversion auto-scan conversion on four channels conversion complete flag or conversion complete interrupt selectable adc clock conversion result justification ? 8-bit truncated mode ? right justified mode ? left justified mode ? left justified sign mode
analog-to-digital converter (adc) features mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor analog-to-digital converter (adc) 233 addr.register name bit 7654321bit 0 $0057 adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $0058 adc clock control register (adiclk) read: adiv2 adiv1 adiv0 adiclk mode1 mode0 00 write: r reset:00000100 $0059 adc data register high 0 (adrh0) read: adx adx adx adx adx adx adx adx write:rrrrrrrr reset:00000000 $005a adc data register low 0 (adrl0) read: adx adx adx adx adx adx adx adx write:rrrrrrrr reset:00000000 $005b adc data register low 1 (adrl1) read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset:00000000 $005c adc data register low 2 (adrl3) read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset:00000000 $005d adc data register low 3 (adrl3) read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset:00000000 $005e adc auto-scan control register (adascr) read: 00000 auto1 auto0 ascan write: reset:00000000 = unimplemented r = reserved figure 15-1. adc i /o register summary
analog-to-digital converter (adc) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 234 analog-to-digital converter (adc) freescale semiconductor 15.4 functional description the adc provides thirteen pins for sampling extern al sources at pins pta0/atd2?pta5/atd7, ptc3 /atd8?ptc7/atd12, and opin1?opin2; one internal source from the analog module. an analog multiplexer allows the single adc co nverter to select one of fourteen adc channels as adc voltage in (v adin ). v adin is converted by the successive approximation register- based analog-to-digital converter. when the conversion is completed, adc places the result in the adc data register, high and low byte (ad rh0 and adrl0), and sets a flag or generates an interrupt. an additional three adc data registers (adrl1?adrl3) are available to store the individual c onverted data for adc channels atd1?atd3 when the auto-scan mode is enabled. data fr om channel atd0 is stored in adrl0 in the au to-scan mode. figure 15-2 shows the structur e of the adc module. 15.4.1 adc port i/o pins pta0?pta5 and ptc3?ptc7 are gener al-purpose i/o pins that are shared with the adc channels, opin 1 and opin2 are tw o analog inputs that are always connect ed to the adc channel se lect multiplexer. the channel select bits, adch [4:0], define which a dc channel/port pin will be used as the input si gnal. the adc overrides t he port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and ca n be used as general- purpose i/o pins. writes to the port data regi ster or data direction register will not have an y affect on the port pin t hat is selected by the adc. read of a port pi n which is in use by t he adc will return the pin condition if the corresponding ddr bit is at logic 0. if the ddr bit is at logic 1, the value in t he port data latch is read.
analog-to-digital converter (adc) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor analog-to-digital converter (adc) 235 15.4.2 voltage conversion when the input voltage to the adc equals v refh , the adc converts the signal to $3ff (full scale). if the input voltage equals v refl , the adc converts it to $000. input voltages between v refh and v refl is a straight-line linear conversi on. all other input voltages will result in $3ff if greater than v refh and $000 if less than v refl . note: input voltage should not exceed the analog supply voltages. figure 15-2. adc block diagram adc data registers internal data bus read ddrax/ddrcx write ddrax/ddrcx reset write ptax/ptcx read ptax/ptcx ptax/ptcx ddrax/ddrcx ptax/ptcx interrupt logic channel select adc clock generator conversion complete adc (v adin ) adciclk cgmxclk bus clock ascan disable disable (11 channels) adiv[2:0] adiclk voltage in opin1 opin2 opout v refl v refh from analog module adch[4:0] atd2?atd12 mux 2-bit up-counter coco aien adrh0 adrl1 adrl0 adrl2 adrl3 auto[1:0]
analog-to-digital converter (adc) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 236 analog-to-digital converter (adc) freescale semiconductor 15.4.3 conversion time conversion starts after a write to the adscr. one conversion will take between 16 and 17 adc clo ck cycles, therefore: the adc conversion time is determine d by the clock so urce chosen and the divide ratio selected. the clock s ource is either the bus clock or cgmxclk and is selectable by the ad iclk bit located in the adc clock register. the divide ratio is selected by the adiv[2:0] bits. for example, if a 4mhz cgmxclk is selected as th e adc input clock source, with a divide-by-four presca le, and the bus speed is set at 2mhz: note: the adc frequency must be between f adic minimum and f adic maximum to meet adc specifications. (see 24.12 5.0v adc electrical characteristics .) since an adc cycle may comprised of several bus cycles (two in the previous example) and t he start of a conversion is initiated by a bus cycle write to the adscr, from zero to two additional bus cycles may occur before the start of the in itial adc cycle. this resu lts in a fractional adc cycle and is represented as the 17th cycle. note: when opout is selected as the adc input, v adin , the conversion time is the accumulation of the op-amp settling time and the normal adc conversion time. after writing to th e adscr to initiate a conversion cycle, the adc module se nds a signal to the analog module for a opout output. a signal will be sent back to the adc by the analog module to indicate that opout sig nal is ready for sampling. upon receiving this signal, t he adc module starts its normal conver sion cycle. (see 24.12 5.0v adc elect rical characteristics .) 16 to17 adc cycles conversion time = adc frequency number of bus cycles = conversion time bus frequency 16 to17 adc cycles conversion time = 4mhz 4 number of bus cycles = 16 s 2mhz = 32 to 34 cycles = 16 to 17 s
analog-to-digital converter (adc) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor analog-to-digital converter (adc) 237 15.4.4 continuous conversion in the continuous conv ersion mode, the adc cont inuously converts the selected channel, filling the adc data register with new data after each conversion. data from the previous conversion will be overwritten whether that data has been read or not . conversions will continue until the adco bit is cl eared. the coco bit is set after each conversion and can be cleared by writing to the adc status and control register or reading of the adr l0 data register. 15.4.5 auto-scan mode in auto-scan mode, t he adc input channel is selected by the value of the 2-bit up-counter, instead of the channel select bits, adch[4:0]. the value of the counter also defines t he data register adrlx to be used to store the conversion re sult. when ascan bit is set, a write to adc status and control regist er (adscr) will reset the auto-scan up-counter and adc conversion will start on the channel 0 up to the channel number defined by the integer va lue of auto[1:0]. after a channel conversion is completed, data is stor ed in adrlx and the co co-bit will be set. the counter value will be incremented by 1 and a new conver sion will start. this process will conti nue until the counter value reaches the value of auto[1:0]. when this happen s, it indicates that the current channel is the last channel to be converted. upon the completi on on the last channel, the counter value will not be incremented and no further conversion will be performed. to sta rt another auto-scan cycle, a write to adscr must be performed. note: the system only provides 8-bit data storage in auto-scan code, user must clear mode[1:0] bits to se lect 8-bit truncation mode before entering auto-scan mode. it is recommended that user s hould disable the auto-scan function before switching channel and al so before entering stop mode.
analog-to-digital converter (adc) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 238 analog-to-digital converter (adc) freescale semiconductor 15.4.6 result justification the conversion result may be form atted in four different ways. left justified right justified left justified sign data mode 8-bit truncation all four of these modes are controlled using mode0 and mode1 bits located in the adc clock c ontrol register (adiclk). left justification wi ll place the eight most signi ficant bits (msb) in the corresponding adc data regi ster high (adrh). this ma y be useful if the result is to be treated as an 8-bit result where the l east significant two bits, located in the adc data register low ( adrl) can be ignored. however, you must read adrl after ad rh or else the in terlocking will prevent all new conver sions from being stored. right justification will place only t he two msbs in the corresponding adc data register high (adrh) and the ei ght lsb bits in adc data register low (adrl). this mode of operation typically is us ed when a 10-bit unsigned result is desired. left justified sign data mode is simi lar to left justified mode with one exception. the msb of the 10-bit result, ad9 located in adrh is complemented. this m ode of operation is useful when a result, represented as a signed magnit ude from mid-scale, is needed. finally, 8-bit truncatio n mode will place the ei ght msbs in adc data register low (adrl). the two lsbs are dropped. this m ode of operation is used when compatibility with 8- bit adc designs ar e required. no interlocking between adrh and adrl is present.
analog-to-digital converter (adc) interrupts mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor analog-to-digital converter (adc) 239 15.4.7 data register interlocking reading adrh in any 10-bit mode latc hes the contents of adrl until adrl is read. until adrl is read all subsequent adc results will be lost. this register interlocking can also be reset by a write to the adc status and control register, or adc clock control regist er. a power-on reset or reset will also clear the interlocking. note that an external conversion request will not reset the lock. 15.4.8 monotonicity the conversion process is monot onic and has no missing codes. 15.5 interrupts when the aien bit is se t, the adc module is capable of generating a cpu interrupt after each adc co nversion or after an auto-scan conversion cycle. a cpu interrupt is generated if the coco bit is at logic 0. the coco bit is not used as a conversion comp lete flag when interrupts are enabled. the inte rrupt vector is defined in table 2-1 . vector addresses . 15.6 low-power modes the stop and wait instructions put the mcu in low power- consumption standby modes. 15.6.1 wait mode the adc continues norma l operation in wait mode. any enabled cpu interrupt request from t he adc can bring the mcu out of wait mode. if the adc is not required to bring th e mcu out of wait mode, power down the adc by setting the adch[4:0] bits to logic 1?s bef ore executing the wait instruction.
analog-to-digital converter (adc) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 240 analog-to-digital converter (adc) freescale semiconductor 15.6.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conver sions resume when the mcu exits stop mode. allow one conver sion cycle to stabilize the analog circuitry before attempting a new adc conversion af ter exiting stop mode. 15.7 i/o signals the adc module has fourteen cha nnels, eleven channels are shared with port a and port c i/o pins; two channels are analog pins, opin1 and opin2, that are sh ared with the analog module; and one channel, opout, from t he analog module. 15.7.1 adc voltage in (v adin ) v adin is the input voltage signal from one of the fourteen channel s to the adc module. 15.7.2 adc analog power pin (v dda ) the adc analog portion uses v dda as its power pi n. connect the v dda pin to the same vo ltage potential as v dd . external filtering may be necessary to ensure clean v dda for good results. note: route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 15.7.3 adc analog ground pin (v ssa ) the adc analog portion uses v ssa as its ground pin. connect the v ssa pin to the same vo ltage potential as v ss .
analog-to-digital converter (adc) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor analog-to-digital converter (adc) 241 15.7.4 adc voltage reference high pin (v refh ) v refh is the power supply for sett ing the reference voltage v refh . connect the v refh pin to the same voltage potential as v dda . there will be a finite current associated with v refh (see section 24. electrical specifications ). note: route v refh carefully for maximum nois e immunity and place bypass capacitors as close as possible to the package. 15.7.5 adc voltage reference low pin (v refl ) v refl is the lower reference supp ly for the adc. connect the v refl pin to the same voltage potential as v ssa . there will be a finite current associated with v refl (see section 24. electri cal specifications ). 15.8 i/o registers these i/o registers control and monitor adc operation: adc status and contro l register (adscr) ? $0057 adc clock control regi ster (adiclk) ? $0058 adc data register high 0 (adrh0) ? $0059 adc data register low 0 (adrl0) ? $005a adc data register low 1 (adrl1) ? $005b adc data register low 2 (adrl2) ? $005c adc data register low 3 (adrl3) ? $005d adc auto-scan control register ( adascr) ? $005e
analog-to-digital converter (adc) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 242 analog-to-digital converter (adc) freescale semiconductor 15.8.1 adc status and control register function of the adc stat us and control register is described here. coco ? conversions complete bit when the aien bit is a l ogic 0, the coco is a read-only bit which is set each time a conversion is comple ted. this bit is cleared whenever the adscr is written, or whenever the adc clo ck control register is written, or whenever the adc data register low, adrlx, is read. if the aien bit is logi c 1, the coco bit alwa ys read as logic 0. adc interrupt will be generated at the end if an adc conversion. reset clears the coco bit. 1 = conversion comp leted (aien = 0) 0 = conversion not completed (aie n = 0)/cpu inte rrupt (aien=1) aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cleared when t he data register, adr0, is read or the a dscr is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert sa mples continuously and update the adc data register at t he end of each conversion. only one conversion is allowed when this bit is cl eared. reset clear s the adco bit. 1 = continuous adc conversion 0 = one adc conversion this bit should not be set when auto-scan mode is enabled; i.e. when ascan=1. address: $0057 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 = unimplemented figure 15-3. adc status and contro l register (adscr)
analog-to-digital converter (adc) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor analog-to-digital converter (adc) 243 adch[4:0] ? adc channel select bits adch[4:0] form a 5-bit field which is used to select one of the adc channels when not in au to-scan mode. the five channel select bits are detailed in table 15-1 . note: care should be taken when using a port pin as both an analog and a digital input simultaneous ly to prevent switchin g noise from corrupting the analog signal. note: recovery from the disabled stat e requires one conversion cycle to stabilize. table 15-1. mux channel select adch4 adch3 adch2 ad ch1 adch0 adc channel input select 00000 atd0 opin1 00001 atd1 opin2 00010 atd2 pta0 00011 atd3 pta1 00100 atd4 pta2 00101 atd5 pta3 00110 atd6 pta4 00111 atd7 pta5 01000 atd8 ptc3 01001 atd9 ptc4 01010 atd10 ptc5 01011 atd11 ptc6 01100 atd12 ptc7 01 1 0 1 at d 1 3 opout 01000 at d 1 4 at d 2 8 reserved 11100 11 1 0 1 at d 2 9 v refh (see note 2) 11 1 1 0 at d 3 0 v refl (see note 2) 11 1 1 1 adc powered-off ? notes: 1. if any unused channels are selected, th e resulting adc conversion will be unknown. 2. the voltage levels supplied from inte rnal reference nodes as specified in th e table are used to verify the operation of the adc converter both in production test and for user applications.
analog-to-digital converter (adc) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 244 analog-to-digital converter (adc) freescale semiconductor 15.8.2 adc clock control register the adc clock control regi ster (adiclk) selects the clock frequency for the adc. adiv[2:0] ? adc clock prescaler bits adiv2, adiv1, and adiv0 form a 3-bit field wh ich selects the divide ratio used by the adc to generate the internal adc clock. table 15-2 shows the available clock configurations. the adc clock should be set to between 500khz and 2mhz. adiclk ? adc input clock select bit adiclk selects either bus clock or cgmxclk as the input clock source to generate the internal adc clock. reset selects cgmxclk as the adc clock source. address: $0058 read: adiv2 adiv1 adiv0 adiclk mode1 mode0 00 write: r reset:00000100 = unimplemented r = reserved figure 15-4. adc clock co ntrol register (adiclk) table 15-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1 x x adc input clock 16 x = don?t care
analog-to-digital converter (adc) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor analog-to-digital converter (adc) 245 if the external clock (cgmxclk) is equal to or greater than 1mhz, cgmxclk can be used as the cl ock source for the adc. if cgmxclk is less than 1mhz, use the pll-generated bus clock as the clock source. as long as t he internal adc clock is at f adic , correct operation can be guaranteed. 1 = internal bus clock 0 = external clock, cgmxclk mode1 and mode0 ? modes of result justification mode1 and mode0 selects between four modes of operation. the manner in which the adc conversion re sults will be placed in the adc data registers is controlled by t hese modes of operation. reset returns right-justified mode. table 15-3. adc mode select mode1 mode0 justification mode 0 0 8-bit truncated mode 0 1 right justified mode 1 0 left justified mode 1 1 left justified sign data mode cgmxclk or bus frequency f adic = adiv[2:0]
analog-to-digital converter (adc) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 246 analog-to-digital converter (adc) freescale semiconductor 15.8.3 adc data regi ster 0 (adrh0 and adrl0) the adc data register 0 consist of a pair of 8-bit regi sters: high byte (adrh0), and low byte (adrl 0). this pair form a 16- bit register to store the 10-bit adc result for the sele cted adc result justification mode. in 8-bit truncated mode, the adrl0 ho lds the eight most significant bits (msbs) of the 10-bit result. the adrl0 is updated each time an adc conversion completes. in 8-bit truncated mode, adrl0 contains no interlocking with adrh0. (see figure 15-5 . adrh0 and adrl0 in 8- bit truncated mode .) in right justified mode the adrh 0 holds the two msbs, and the adrl0 holds the eight least sign ificant bits (lsbs), of th e 10-bit result. adrh0 and adrl0 are updated each time a single channel adc conversion completes. reading adrh0 latches the contents of adrl0. until adrl0 is read all subsequen t adc results will be lost. (see figure 15-6 . adrh0 and adrl0 in right justified mode .) addr.register name bit 7654321bit 0 $0059 adc data register high 0 (adrh0) read: 00000000 write:rrrrrrrr reset:00000000 $005a adc data register low 0 (adrl0) read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset:00000000 figure 15-5. adrh0 and adr l0 in 8-bit truncated mode addr.register name bit 7654321bit 0 $0059 adc data register high 0 (adrh0) read: 000000ad9ad8 write:rrrrrrrr reset:00000000 $005a adc data register low 0 (adrl0) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write:rrrrrrrr reset:00000000 figure 15-6. adrh0 and adrl0 in right justified mode
analog-to-digital converter (adc) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor analog-to-digital converter (adc) 247 in left justified mode the adrh0 holds the eight most significant bits (msbs), and the adrl0 holds the two least significant bits (lsbs), of the 10-bit result. the adrh0 and a drl0 are updated each time a single channel adc conversion complete s. reading adrh 0 latches the contents of adrl0. until adrl0 is read all s ubsequent adc results will be lost. (see figure 15-7 . adrh0 and a drl0 in left justified mode .) in left justified sign mode the adrh 0 holds the eight msbs with the msb complemented, and the a drl0 holds the two leas t significant bits (lsbs), of the 10-bit result. the adrh0 and adrl0 ar e updated each time a single channel adc conversion completes. reading adrh0 latches the contents of adrl0. un til adrl0 is read all subsequent adc results will be lost. (see figure 15-8 . adrh0 and adrl0 in left justified sign data mode .) addr.register name bit 7654321bit 0 $0059 adc data register high 0 (adrh0) read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset:00000000 $005a adc data register low 0 (adrl0) read: ad1 ad0 000000 write:rrrrrrrr reset:00000000 figure 15-7. adrh0 and adrl0 in left justified mode addr.register name bit 7654321bit 0 $0059 adc data register high 0 (adrh0) read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset:00000000 $005a adc data register low 0 (adrl0) read: ad1 ad0 000000 write:rrrrrrrr reset:00000000 figure 15-8. adrh0 and adrl0 in left justified sign data mode
analog-to-digital converter (adc) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 248 analog-to-digital converter (adc) freescale semiconductor 15.8.4 adc auto-scan mode data registers (adrl1?adrl3) the adc data registers 1 to 3 (adrl 1?adrl3), are 8-bit registers for conversion results in 8-bit truncat ed mode, for channels atd1 to atd3, when the adc is ope rating in auto-scan m ode (mode[1:0] = 00). 15.8.5 adc auto-scan c ontrol register (adascr) the adc auto-scan control register (adascr) enables an d controls the adc auto-scan function. auto[1:0] ? auto-scan mo de channel select bits auto1 and auto0 form a 2-bit fiel d which is used to define the number of auto-scan channels us ed when in auto-scan mode. reset clears these bits. address: adrl1, $005b; adrl2, $005c; and adrl3, $005d read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset:00000000 r=reserved figure 15-9. adc data regist er low 1 to 3 (adrl1?adrl3) address: $005e read: 00000 auto1 auto0 ascan write: reset:00000000 = unimplemented r = reserved figure 15-10. adc scan control r egister (adascr) table 15-4. auto-scan mode channel select auto1 auto0 auto-scan channels 0 0 atd0 only 0 1 atd0 to atd1 1 0 atd0 to atd2 1 1 atd0 to atd3
analog-to-digital converter (adc) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor analog-to-digital converter (adc) 249 ascan ? auto-scan mode enable bit this bit enable/disable t he auto-scan mode. rese t clears this bit. 1 = auto-scan mode is enabled 0 = auto-scan mode is disabled auto-scan mode should not be enabled when adc continuous conversion is enabled; i.e. when adco=1.
analog-to-digital converter (adc) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 250 analog-to-digital converter (adc) freescale semiconductor
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 251 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 16. serial communications interface (sci) 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 16.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 16.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 16.5.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 16.5.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 16.5.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 16.5.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 259 16.5.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 16.5.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 16.5.2.5 inversion of transm itted output. . . . . . . . . . . . . . . . . . . 261 16.5.2.6 transmitter in terrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .261 16.5.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 16.5.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 16.5.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 16.5.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 16.5.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 16.5.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .266 16.5.3.6 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 16.5.3.7 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 16.5.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 16.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 16.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 16.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 16.7 sci during break module interrupts. . . . . . . . . . . . . . . . . . . .272 16.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 16.8.1 txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 252 serial communications interface (sci) freescale semiconductor 16.8.2 rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 16.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 16.9.1 sci control regi ster 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 16.9.2 sci control regi ster 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 16.9.3 sci control regi ster 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 16.9.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 16.9.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 16.9.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 16.9.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . .288 16.2 introduction this section describes the serial communications interface (sci) module, which allows hi gh-speed asynchronous communications with peripheral devices and other mcus. note: when the sci is enabled, the txd pin is an open-drain output and requires a pullup resistor to be connected for pr oper sci operation. note: references to dma (direct-memory access) and associated functions are only valid if t he mcu has a dma module. this mcu does not have the dma function. any dma -related register bits sh ould be left in their reset state for normal mcu operation. 16.3 features features of the sci modu le include the following: full-duplex operation standard mark/space non-re turn-to-zero (nrz) format 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled trans mitter and receiver separate receiver and transmi tter cpu interrupt requests programmable transm itter output polarity
serial communications interface (sci) features mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 253 two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framin g error detection hardware parity checking 1/16 bit-time noise detection configuration register bit, scibdsrc, to al low selection of baud rate clock source
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 254 serial communications interface (sci) freescale semiconductor 16.4 pin name conventions the generic names of th e sci i/o pins are: rxd (receive data) txd (transmit data) sci i/o (input/outpu t) lines are implemented by sharing parallel i/o port pins. the full name of an sci input or output re flects the name of the shared port pin. table 16-1 shows the full names and the generic names of the sci i/o pins. the generic pin names appear in the text of this section. note: when the sci is enabled, the txd pin is an open-drain output and requires a pullup resistor to be connected for pr oper sci operation. 16.5 functional description figure 16-1 shows the structure of the sc i module. the sci allows full- duplex, asynchronous, nrz serial communication among the mcu and remote devices, including other mcus . the transmitter and receiver of the sci operate independent ly, although they us e the same baud rate generator. during normal oper ation, the cpu monitors the status of the sci, writes the data to be transmi tted, and processes received data. the baud rate clock source for the sci can be selected via the configuration bit, scibd src, of the config2 regi ster ($001d). source selection values are shown in figure 16-1 . table 16-1. pin name conventions generic pin names: rxd txd full pin names: ptb3/scl1/rxd ptb2/sda1/txd
serial communications interface (sci) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 255 figure 16-1. sci m odule block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 dmate orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register dma interrupt control transmitter interrupt control receiver interrupt control error interrupt control control dmare ensci loops ensci internal bus txinv loops 4 16 pre- scaler baud divider cgmxclk it12 a b sl x scibdsrc from sl = 0 => x = a sl = 1 => x = b config rxd txd cgmxclk is from cgm module it12 = f bus
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 256 serial communications interface (sci) freescale semiconductor addr.register name bit 7654321bit 0 $0013 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $0014 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 sci control register 3 (scc3) read: r8 t8 dmare dmate orie neie feie peie write: reset:uu000000 $0016 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 sci status register 2 (scs2) read: bkf rpf write: reset:00000000 $0018 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved u = unaffected figure 16-2. sci i/o register summary
serial communications interface (sci) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 257 16.5.1 data format the sci uses the standard non-return-to-zero mark /space data format illustrated in figure 16-3 . figure 16-3. sci data formats 16.5.2 transmitter figure 16-4 shows the structure of the sci transmitter. the baud rate clock source for the sci can be selected via the configuration bit, scibdsr c. source selection values are shown in figure 16-4 . bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format bit m in scc1 clear start bit bit 0 next stop bit start bit 9-bit data format bit m in scc1 set bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity bit parity bit
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 258 serial communications interface (sci) freescale semiconductor figure 16-4. sci transmitter dmate scte pen pty h876543210l 11-bit transmit stop start t8 dmate scte sctie tcie sbk tc parity generation msb sci data register load from scdr shift enable preamble all 1s break all 0s transmitter control logic shift register dmate tc sctie tcie scte transmitter cpu int errupt request transmitter dma service request m ensci loops te txinv internal bus 4 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider 16 sctie cgmxclk it12 a b sl x sl = 0 => x = a sl = 1 => x = b scibdsrc from config2 txd
serial communications interface (sci) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 259 16.5.2.1 character length the transmitter can accommod ate either 8-bit or 9- bit data. the state of the m bit in sci control register 1 (scc1) deter mines character length. when transmitting 9-bit data, bit t8 in sci control register 3 (scc3) is the ninth bi t (bit 8). 16.5.2.2 character transmission during an sci transmission, the transmit shift regist er shifts a character out to the txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the tr ansmit shift register. to initiate an sci transmission: 1. enable the sci by writing a logi c 1 to the enable sci bit (ensci) in sci control r egister 1 (scc1). 2. enable the transmitter by writi ng a logic 1 to the transmitter enable bit (te) in sci cont rol register 2 (scc2). 3. clear the sci transmit ter empty bit by first reading sci status register 1 (scs1) and t hen writing to the scdr. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, tran smitter control logic automatically loads the transmit shift register with a preamble of logic 1s. after the preamble shifts out, control logic tr ansfers the scdr data into the transmit shift register. a logic 0 start bit automati cally goes into the least significant bit position of the transmit shift register. a lo gic 1 stop bit goes into the most signi ficant bit position. the sci transmitter empt y bit, scte, in scs1 becomes set when the scdr transfers a byte to the trans mit shift register. the scte bit indicates that the scdr c an accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmi tter cpu interrupt request. when the transmit shift register is not transmitting a character, the txd pin goes to the idle cond ition, logic 1. if at an y time software clears the ensci bit in sci control register 1 (scc1), the transmitter and receiver relinquish control of the port pin.
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 260 serial communications interface (sci) freescale semiconductor 16.5.2.3 break characters writing a logic 1 to the send break bit, sbk, in scc2 loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1. as long as sbk is at logi c 1, transmitter logic continuously loads break characters in to the transmit shif t register. after software clears the sbk bit, the shif t register finishes transmitting the last break character and then tr ansmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the nex t character. the sci recognizes a break characte r when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has these effects on sci registers: sets the framing erro r bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci dat a register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception in prog ress flag (rpf) bits 16.5.2.4 idle characters an idle character contains all logic 1s and has no st art, stop, or parity bit. idle character length depends on the m bit in scc1. th e preamble is a synchronizing idle character that begins every transmission. if the te bit is clear ed during a transmission, th e txd pin becomes idle after completion of th e transmission in prog ress. clearing and then setting the te bit duri ng a transmission queues an id le character to be sent after the character currently being transmitted.
serial communications interface (sci) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 261 note: when queueing an idle character, return the te bit to logic 1 before the stop bit of the current c haracter shifts out to the txd pin. setting te after the stop bit appears on txd causes da ta previously wr itten to the scdr to be lost. toggle the te bit for a queued idle character when the scte bit becomes set and just be fore writing the nex t byte to the scdr. 16.5.2.5 inversion of transmitted output the transmit inversion bit (txinv) in sci control r egister 1 (scc1) reverses the polarity of transmitted da ta. all transmitted values, including idle, break, start, and stop bits, are inverted when txinv is at logic 1. (see 16.9.1 sci control register 1 .) 16.5.2.6 transmitter interrupts these conditions can ge nerate cpu interrupt requests from the sci transmitter: sci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can gene rate a transmitter cp u interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generat e transmitter cpu interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are em pty and that no break or idle character has been generated. th e transmission complete interrupt enable bit, tcie , in scc2 enables the tc bit to generate transmitter cpu interrupt requests.
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 262 serial communications interface (sci) freescale semiconductor 16.5.3 receiver figure 16-5 shows the structure of the sci receiver. 16.5.3.1 character length the receiver can accommodat e either 8-bit or 9-bi t data. the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bit data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when rece iving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 16.5.3.2 character reception during an sci re ception, the receive shift regi ster shifts characters in from the rxd pin. the sci data register ( scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive shift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status regi ster 1 (scs1) becomes se t, indicating that the received byte can be read. if the sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bi t generates a receiver cpu interrupt request.
serial communications interface (sci) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 263 figure 16-5. sci receiver block diagram all 1s all 0s m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery dmare scrf or orie nf neie fe feie pe peie dmare scrie scrf ilie idle wakeup logic parity checking msb error cpu interrupt request dma service request cpu interrupt request sci data register r8 dmare orie neie feie peie scrie ilie rwu scrf idle or nf fe pe internal bus pre- scaler baud divider 4 16 scp1 scp0 scr2 scr1 scr0 scrie dmare cgmxclk it12 a b sl x scibdsrc from sl = 0 => x = a sl = 1 => x = b config2 rxd
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 264 serial communications interface (sci) freescale semiconductor 16.5.3.3 data sampling the receiver samples the rxd pin at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at the following times (see figure 16-6 ): after every start bit after the receiver detects a data bit change from l ogic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of t he next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an asyn chronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 16-6. receiver data sampling rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb rxd
serial communications interface (sci) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 265 to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 16-2 summarizes t he results of the start bit verification samples. start bit verification is not successful if any two of the three verification samples are logic 1s. if start bit ve rification is not successful, the rt clock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at r t8, rt9, and rt10. table 16-3 summarizes the results of the data bit samples. table 16-2. start bit verification rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 table 16-3. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 266 serial communications interface (sci) freescale semiconductor note: the rt8, rt9, and rt10 samp les do not affect star t bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verifica tion, the noise flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 16-4 summarizes the resu lts of the stop bit samples. 16.5.3.4 framing errors if the data recovery l ogic does not detect a logi c 1 where the stop bit should be in an in coming character, it sets t he framing error bit, fe, in scs1. a break character also sets t he fe bit because a break character has no stop bit. the fe bit is set at the same time that t he scrf bit is set. 16.5.3.5 baud rate tolerance a transmitting device may be operat ing at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. then a noise error occurs. if more t han one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate table 16-4. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0
serial communications interface (sci) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 267 tolerance is much more than the degree of misalignm ent that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within characters corrects misali gnments between trans mitter bit times and receiver bit times. slow data tolerance figure 16-7 shows how much a slow received character can be misaligned without causing a noise error or a fr aming error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at r t8, rt9, and rt10. figure 16-7. slow data for an 8-bit character, data sampling of the st op bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 16-7 , the receiver counts 154 rt cycles at the point when the count of t he transmitting device is 9 bit times 16 rt cycles + 3 rt cycles = 147 rt cycles. the maximum percent diff erence between the re ceiver count and the transmitter count of a slow 8- bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 147 ? 154 ------------- ------------ - 100 4.54% =
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 268 serial communications interface (sci) freescale semiconductor with the misaligned character shown in figure 16-7 , the receiver counts 170 rt cycles at the point when the count of t he transmitting device is 10 bit times 16 rt cycles + 3 rt cycles = 163 rt cycles. the maximum percent diff erence between the re ceiver count and the transmitter count of a slow 9- bit character with no errors is fast data tolerance figure 16-8 shows how much a fast received character can be misaligned without causing a noise error or a framing erro r. the fast stop bit ends at rt10 instead of rt16 but is st ill there for t he stop bit data samples at rt8, rt9, and rt10. figure 16-8. fast data for an 8-bit character, data sampling of the st op bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 16-8 , the receiver counts 154 rt cycles at the point when the count of t he transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent diff erence between the re ceiver count and the transmitter count of a fast 8-bi t character with no errors is 170 163 ? 170 ------------- ------------ - 100 4.12% = idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 160 ? 154 ------------- ------------ - 100 3.90% =
serial communications interface (sci) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 269 for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 16-8 , the receiver counts 170 rt cycles at the point when the count of t he transmitting device is 11 bit times 16 rt cycles = 176 rt cycles. the maximum percent diff erence between the re ceiver count and the transmitter count of a fast 9- bit character with no errors is 16.5.3.6 receiver wakeup so that the mcu can ignore tr ansmissions intended only for other receivers in multiple-receiver system s, the receiver can be put into a standby state. setting the receiver wa keup bit, rwu, in scc2 puts the receiver into a standby state during which re ceiver interrupts are disabled. depending on the state of the wake bit in scc1, either of two conditions on the rxd pin can bring the receiver out of the standby state: address mark ? an address mark is a logic 1 in the most significant bit position of a rece ived character. when the wake bit is set, an address mark wakes t he receiver from the standby state by clearing the rwu bit. the addr ess mark also sets the sci receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they ar e the same, the receiv er remains awake and processes the characters that fo llow. if they are not the same, software can set the rwu bit and put the rece iver back into the standby state. idle input line condition ? when the wake bit is clear, an idle character on the rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle char acter that wakes the receiver does not set the receiver idle bit, idle , or the sci receiver 170 176 ? 170 ------------ ------------- - 100 3.53% =
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 270 serial communications interface (sci) freescale semiconductor full bit, scrf. the idle line type bi t, ilty, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. note: with the wake bit clear , setting the rwu bit afte r the rxd pin has been idle may cause the receiver to wake up immediately. 16.5.3.7 receiver interrupts the following sources can gene rate cpu interrupt re quests from the sci receiver: sci receiver full ( scrf) ? the scrf bit in scs1 indicates that the receive shift register has tran sferred a characte r to the scdr. scrf can generate a receiver cp u interrupt request. setting the sci receive interrupt enable bit, s crie, in scc2 enables the scrf bit to generate rece iver cpu interrupts. idle input (idle) ? the idle bit in scs1 i ndicates that 10 or 11 consecutive logic 1s shifted in from the rxd pi n. the idle line interrupt enable bit, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. 16.5.3.8 error interrupts the following receiver error flags in scs1 can generat e cpu interrupt requests: receiver overrun (or) ? the or bit indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. the previous character remains in the scdr, and the new character is lost. the overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. noise flag (nf) ? the nf bit is set when the sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enabl e bit, neie, in scc3 enables nf to generate sci erro r cpu interrupt requests.
serial communications interface (sci) low-power modes mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 271 framing error (fe) ? the fe bit in scs1 is se t when a logic 0 occurs where the receiver expec ts a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. parity error (pe) ? the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in scc3 enables pe to gener ate sci error cpu interrupt requests. 16.6 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. 16.6.1 wait mode the sci module remains active af ter the execution of a wait instruction. in wait m ode, the sci module register s are not accessible by the cpu. any enabled c pu interrupt request fr om the sci module can bring the mcu out of wait mode. if sci module functions are not requ ired during wait mode, reduce power consumption by disabling the m odule before executing the wait instruction. refer to 9.7 low-power modes for information on ex iting wait mode. 16.6.2 stop mode the sci module is inactive after the execution of a st op instruction. the stop instructio n does not affect sci r egister states. sci module operation resumes after an external interrupt. because the internal clock is inacti ve during stop m ode, entering stop mode during an sci transmission or reception results in invalid data. refer to 9.7 low-power modes for information on exiting stop mode.
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 272 serial communications interface (sci) freescale semiconductor 16.7 sci during br eak module interrupts the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during the break state. to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect status bits du ring the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write i/o registers during the break state wi thout affecting status bits. some status bits have a 2-st ep read/write clearing proced ure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 16.8 i/o signals port b shares two of its pins with the sci module. the two sci i/o pins are: ptb2/sda1/txd ? transmit data ptb3/scl1/rxd ? receive data 16.8.1 txd (transmit data) when the sci is enabled (ensci =1), the ptb2/sda1/txd pin becomes the serial data output, txd, from the sci transmitter regardless of the state of the ddrb2 bit in data direction register b (ddrb). the txd pin is an open-drain output and requires a pullup resistor to be connected for proper sci operation. note: the ptb2/sda1/txd pin is an open-drain pin w hen configured as an output. therefore, when configured as a genera l purpose output pin (ptb2), a pullup resistor must be connected to this pin.
serial communications interface (sci) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 273 16.8.2 rxd (receive data) when the sci is enabled (ensci =1), the ptb3/scl1/rxd pin becomes the serial data input, rxd, to the sci receiver r egardless of the state of the ddrb3 bit in data direction re gister b (ddrb). note: the ptb3/scl1/rxd pin is an open-dr ain pin when conf igured as an output. therefore, when configured as a genera l purpose output pin (ptb3), a pullup resistor must be connected to this pin. 16.9 i/o registers these i/o registers control and monitor sci operation: sci control register 1 (scc1) sci control register 2 (scc2) sci control register 3 (scc3) sci status register 1 (scs1) sci status register 2 (scs2) sci data register (scdr) sci baud rate register (scbr) 16.9.1 sci cont rol register 1 sci control register 1: enables loop mode operation enables the sci controls output polarity controls character length controls sci wakeup method controls idle character detection enables parity function controls parity type
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 274 serial communications interface (sci) freescale semiconductor loops ? loop mode select bit this read/write bit enabl es loop mode operatio n. in loop mode the rxd pin is disconnected from the sci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. re set clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable sci bit this read/write bit enabl es the sci and the sc i baud rate generator. clearing ensci sets the scte and tc bits in sc i status register 1 and disables transmitter interrupt s. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter out put not inverted note: setting the txinv bit inve rts all transmitted values , including idle, break, start, and stop bits. address: $0013 bit 7654321bit 0 read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 16-9. sci cont rol register 1 (scc1)
serial communications interface (sci) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 275 m ? mode (character length) bit this read/write bit deter mines whether sci characters are eight or nine bits long. (see table 16-5.) the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wakeup condition bit this read/write bit deter mines which condition wakes up the sci: a logic 1 (address mark) in the most si gnificant bit posi tion of a received character or an idle condition on the rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit deter mines when the sci star ts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but re quires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit c ount begins afte r stop bit 0 = idle character bit c ount begins after start bit pen ? parity enable bit this read/write bi t enables the sci parity function. (see table 16-5.) when enabled, the parity function in serts a parity bit in the most significant bit pos ition. (see figure 16-3.) re set clears the pen bit. 1 = parity function enabled 0 = parity function disabled
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 276 serial communications interface (sci) freescale semiconductor pty ? parity bit this read/write bit determines w hether the sci generates and checks for odd parity or even parity. (see table 16-5.) reset clears the pty bit. 1 = odd parity 0 = even parity note: changing the pty bit in the middle of a transmission or reception can generate a parity error. 16.9.2 sci cont rol register 2 sci control register 2: enables the following cpu interrupt requests: ? enables the scte bit to gener ate transmitter cpu interrupt requests ? enables the tc bi t to generate transmi tter cpu interrupt requests ? enables the scrf bit to gener ate receiver cpu interrupt requests ? enables the idle bit to gene rate receiver cpu interrupt requests table 16-5. character format selection control bits character format m pen and pty start bits data bits parity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 0 10 1 7 even 1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8 even 1 11 bits 1 11 1 8 odd 1 11 bits
serial communications interface (sci) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 277 enables the transmitter enables the receiver enables sci wakeup transmits sci break characters sctie ? sci transmit interrupt enable bit this read/write bi t enables the scte bit to generate sci transmitter cpu interrupt requests. re set clears t he sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ? transmission comple te interrupt enable bit this read/write bit enable s the tc bit to generat e sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? sci receive interrupt enable bit this read/write bi t enables the scrf bit to generate sci receiver cpu interrupt requests. re set clears t he scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to gener ate sci receiver cpu interrupt requests. rese t clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabl ed to generate cp u interrupt requests address: $0014 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 16-10. sci cont rol register 2 (scc2)
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 278 serial communications interface (sci) freescale semiconductor te ? transmitt er enable bit setting this read/write bit begin s the transmission by sending a preamble of 10 or 11 logi c 1s from the transmit shift register to the txd pin. if software clears the te bi t, the transmitter completes any transmission in progress before the tx d returns to the idle condition (logic 1). clearing and then setti ng te during a transmission queues an idle character to be sent af ter the character currently being transmitted. reset clears the te bit. 1 = transmitt er enabled 0 = transmitt er disabled note: writing to the te bit is not allowed when the enab le sci bit (ensci) is clear. ensci is in sci control register 1. re ? receiver enable bit setting this read/write bit enables the receiver. clearing the re bit disables the receiver but does not a ffect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note: writing to the re bit is not allowed w hen the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a st andby state during which receiver interrupt s are disabled. the wake bit in scc1 determines whether an idle input or an address mark brings the receiver out of the standby state and clear s the rwu bit. rese t clears the rwu bit. 1 = standby state 0 = normal operation
serial communications interface (sci) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 279 sbk ? send break bit setting and then clearing this r ead/write bit transmits a break character followed by a logic 1. the logic 1 after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously transmits break characters with no logic 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break charac ters being transmitted note: do not toggle the sbk bi t immediately after se tting the scte bit. toggling sbk before the preamble begins causes the sci to send a break character instead of a preamble. 16.9.3 sci cont rol register 3 sci control register 3: stores the ninth sci data bit rece ived and the ninth sci data bit to be transmitted enables these interrupts: ? receiver overrun interrupts ? noise error interrupts ? framing error interrupts parity error interrupts address: $0015 bit 7654321bit 0 read: r8 t8 dmare dmate orie neie feie peie write: reset:uu000000 = unimplemented u = unaffected figure 16-11. sci cont rol register 3 (scc3)
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 280 serial communications interface (sci) freescale semiconductor r8 ? received bit 8 when the sci is receiving 9-bit char acters, r8 is the read-only ninth bit (bit 8) of the received characte r. r8 is received at the same time that the scdr receiv es the other 8 bits. when the sci is receiving 8-bit charac ters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the sci is transmi tting 9-bit characters , t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift register at the same time that the scdr is loaded into the transmit shift register. re set has no effect on the t8 bit. dmare ? dma receive enable bit caution: the dma module is not included on th is mcu. writing a logic 1 to dmare or dmate may adverse ly affect mcu performance. 1 = dma not enabled to service sci receiver dma service requests generated by the scrf bit (sci receiver cpu interrupt requests enabled) 0 = dma not enabled to service sci receiver dma service requests generated by the scrf bit (sci receiver cpu interrupt requests enabled) dmate ? dma transfer enable bit caution: the dma module is not included on th is mcu. writing a logic 1 to dmare or dmate may adverse ly affect mcu performance. 1 = scte dma service requests enabled; scte cpu interrupt requests disabled 0 = scte dma service requests disabled; scte cpu interrupt requests enabled
serial communications interface (sci) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 281 orie ? receiver overr un interrupt enable bit this read/write bit enabl es sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt r equests from or bit enabled 0 = sci error cpu interrupt r equests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enabl es sci error cpu interrupt requests generated by the noise error bi t, ne. reset clears neie. 1 = sci error cpu interrupt r equests from ne bit enabled 0 = sci error cpu interrupt r equests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enabl es sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt r equests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enables sci receiver cpu interrupt requests generated by the par ity error bit, pe. (see 16.9.4 sci status register 1 .) reset clears peie. 1 = sci error cpu interrupt r equests from pe bit enabled 0 = sci error cpu interrupt r equests from pe bit disabled
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 282 serial communications interface (sci) freescale semiconductor 16.9.4 sci status register 1 sci status register 1 (s cs1) contains flags to signal these conditions: transfer of scdr data to trans mit shift register complete transmission complete transfer of receive shift r egister data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ? sci transmi tter empty bit this clearable, read-only bit is set when the scdr transfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt r equest. in normal operation, clear the sct e bit by reading sc s1 with scte set and then writing to scdr. re set sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register address: $0016 bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 16-12. sci status register 1 (scs1)
serial communications interface (sci) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 283 tc ? transmission complete bit this read-only bit is set when the sc te bit is set, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is automatically cleared when data, preambl e or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency between queuei ng data, preambl e, and break and the transmission actually star ting. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf c an generate an sci receiver cpu interrupt request. w hen the scrie bit in scc2 is set, scrf generates a cpu inte rrupt request. in norm al operation, clear the scrf bit by readi ng scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an sci error cpu interrupt request if the ilie bit in s cc2 is also set. clear the idle bit by reading scs1 with idle set a nd then reading the scdr. after the receiver is enabled, it must receive a valid c haracter that sets the scrf bit before an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character must again set the scrf bit before an idle condition can set the idle bit. rese t clears the idle bit. 1 = receiver input idle 0 = receiver input active (or id le since the idle bit was cleared) or ? receiver overrun bit this clearable, read-only bit is se t when software fails to read the scdr before the receive shift regist er receives the next character. the or bit generates an sci error cpu interrupt request if the orie
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 284 serial communications interface (sci) freescale semiconductor bit in scc3 is also set. the data in the shift regist er is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. rese t clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an over run to occur between reads of scs1 and scdr in the fl ag-clearing sequence. figure 16-13 shows the normal flag- clearing sequence and an example of an overrun caused by a delayed flag-clearin g sequence. the delayed read of scdr does not clear t he or bit because or was not set when scs1 was read. byte 2 caused the ov errun and is lost. the next flag- clearing sequence read s byte 3 in the scd r instead of byte 2. in applications that are subject to software la tency or in which it is important to know which byte is lost due to an ov errun, the flag- clearing routine c an check the or bit in a se cond read of scs1 after reading the data register. nf ? receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the rxd pin. nf generates an nf cpu inte rrupt request if the neie bit in scc3 is also set. clear the nf bit by reading sc s1 and then reading the scdr. reset cl ears the nf bit. 1 = noise detected 0 = no noise detected fe ? receiver framing error bit this clearable, read-only bit is set when a logic 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected
serial communications interface (sci) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 285 figure 16-13. fl ag clearing sequence pe ? receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is al so set. clear the pe bit by reading scs1 with pe set and then readi ng the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 286 serial communications interface (sci) freescale semiconductor 16.9.5 sci status register 2 sci status register 2 co ntains flags to signal the following conditions: break character detected incoming data bkf ? break flag bit this clearable, read-only bit is set when the sci detects a break character on the rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bi t in scc3 is cleared. bkf does not generate a cpu interrupt r equest. clear bkf by reading scs2 with bkf set and then readi ng the scdr. once cleared, bkf can become set again only after logic 1s again appear on the rxd pin followed by another br eak character. reset clears the bkf bit. 1 = break character detected 0 = no break ch aracter detected rpf ? reception in progress flag bit this read-only bit is set when the receiver detec ts a logic 0 during the rt1 time period of t he start bit search. rp f does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. pol ling rpf before disabling the sci module or entering stop mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress address: $0017 bit 7654321bit 0 read: bkf rpf write: reset:00000000 = unimplemented figure 16-14. sci status register 2 (scs2)
serial communications interface (sci) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 287 16.9.6 sci data register the sci data register (scdr) is the buffer between the internal data bus and the receive and transmit shift r egisters. reset has no effect on data in the sci data register. r7/t7?r0/t0 ? receive/transmit data bits reading the sci data register (scdr) accesses the read-only received data bits, r7:r0. writing to the scdr writ es the data to be transmitted, t7:t0. reset has no effect on the scdr. note: do not use read/modify/write inst ructions on the sci data register. address: $0018 bit 7654321bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 16-15. sci data register (scdr)
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 288 serial communications interface (sci) freescale semiconductor 16.9.7 sci baud rate register the baud rate register (scbr) selects the baud rate for bo th the receiver and the transmitter. scp1 and scp0 ? sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 16-6 . reset clears scp1 and scp0. scr2?scr0 ? sci baud rate select bits these read/write bits select the sc i baud rate divisor as shown in table 16-7 . reset clears scr2?scr0. address: $0019 bit 7654321bit 0 read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved figure 16-16. sci baud rate register (scbr) table 16-6. sci baud rate prescaling scp1 and scp0 prescaler divisor (pd) 00 1 01 3 10 4 11 13
serial communications interface (sci) i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor serial communications interface (sci) 289 use this formula to calc ulate the sci baud rate: where: sci clock source = f bus or cgmxclk (selected by scibdsrc bi t in config2 register) pd = prescaler divisor bd = baud rate divisor table 16-8 shows the sci baud rates that can be generated with a 4.9152-mhz bus clock when f bus is selected as sci clock source. table 16-7. sci baud rate selection scr2, scr1, and scr0 baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate sci clock source 64 pd bd ---------------- -------------- -------------- - =
serial communications interface (sci) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 290 serial communications interface (sci) freescale semiconductor table 16-8. sci baud ra te selection examples scp1 and scp0 prescaler divisor (pd) scr2, scr1, and scr0 baud rate divisor (bd) baud rate (f bus = 4.9152 mhz) 00 1 000 1 76,800 00 1 001 2 38,400 00 1 010 4 19,200 00 1 011 8 9600 00 1 100 16 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25,600 01 3 001 2 12,800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19,200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5908 11 13 001 2 2954 11 13 010 4 1477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 291 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 17. multi-master iic interface (mmiic) 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.5 multi-master iic system configuratio n . . . . . . . . . . . . . . . . . . 295 17.6 multi-master iic bus prot ocol . . . . . . . . . . . . . . . . . . . . . . . . . 295 17.6.1 start signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 17.6.2 slave address transmission . . . . . . . . . . . . . . . . . . . . . . .296 17.6.3 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 17.6.4 repeated start signal . . . . . . . . . . . . . . . . . . . . . . . . . . 297 17.6.5 stop signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 17.6.6 arbitration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 17.6.7 clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 17.6.8 handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 17.6.9 packet error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.7 mmiic i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.7.1 mmiic address register (mmadr) . . . . . . . . . . . . . . . . . . 299 17.7.2 mmiic control register 1 (mmcr1) . . . . . . . . . . . . . . . . . 301 17.7.3 mmiic control register 2 (mmcr2) . . . . . . . . . . . . . . . . . 303 17.7.4 mmiic status register (mmsr). . . . . . . . . . . . . . . . . . . . . 305 17.7.5 mmiic data transmit register (mmdtr) . . . . . . . . . . . . . 307 17.7.6 mmiic data receive register (m mdrr). . . . . . . . . . . . . . 308 17.7.7 mmiic crc data register (mm crcdr). . . . . . . . . . . . . . 309 17.7.8 mmiic frequency divider register (mmfdr) . . . . . . . . . . 310 17.8 program algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 17.8.1 data sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 17.9 smbus protocols with pec and with out pec. . . . . . . . . . . . . 313
multi-master iic interface (mmiic) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 292 multi-master iic interface (mmiic) freescale semiconductor 17.9.1 quick command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 17.9.2 send byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 17.9.3 receive byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 17.9.4 write byte/word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 17.9.5 read byte/word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 17.9.6 process call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 17.9.7 block read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 17.10 smbus protocol implementation . . . . . . . . . . . . . . . . . . . . . . 316 17.2 introduction the multi-master iic (mmiic) interface is a two wire, bidirectional serial bus which provides a simple, ef ficient way for data exchange between devices. the interface is designed for internal serial communication between the mcu and other iic devi ces. it has har dware generated start and stop signals; and byte by byte interrupt driven software algorithm. this bus is suitable for appl ications which need frequent communications over a short distanc e between a number of devices. it also provides a flexibility that allo ws additional devices to be connected to the bus. the maximu m data rate is 100k-bps, and the maximum communication distance and number of devices that can be connected is limited by a maximum bus capacitance of 400pf. this mmiic interface is also smbu s (system management bus) version 1.0 and 1.1 compatible, with hard ware cyclic redundancy code (crc) generation, making it suitable fo r smart battery applications. for connection flex ibility, two channel s are available: channel 0 ? sda0 and scl0 channel 1 ? sda1 and scl1 the two channels are multiplexed; only o ne channel is active at any one time.
multi-master iic interface (mmiic) features mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 293 17.3 features features of the m mic module include: full smbus version 1.0/1.1 compliance multi-master iic bus standard software programmable for one of eight different serial clock frequencies software controllable a cknowledge bit generation interrupt driven byte by byte data transfer calling address iden tification interrupt arbitration loss detec tion and no-ack awaren ess in master mode and automatic mode switching from master to slave auto detection of r/w bit and switching of transmit or receive mode accordingly detection of start, repeat ed start, and stop signals auto generation of start and stop condition in master mode repeated start generation master clock generator with eight selectable baud rates automatic recognition of th e received acknowledge bit busy detection software enabled 8-bit crc generation/decoding 17.4 i/o pins the mmiic module uses four i/o pi ns, shared with standard port i/o pins. the full name of the m miic i/o pins are listed in table 17-1 . the generic pin name appear in t he text that follows. the sda0/scl0 and sda1/scl1 pins ar e open-drain. when configured as general purpose output pins (ptb 0?ptb3), pullup resistors must be connected to these pins.
multi-master iic interface (mmiic) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 294 multi-master iic interface (mmiic) freescale semiconductor table 17-1. pin name conventions mmiic generic pin names: full mcu pin names: pin selected for mmiic function by: sda0 ptb0/sda0 mmen and sdascl1 bits in mmcr1 ($0049) scl0 ptb1/scl0 sda1 ptb2/sda1/txd ensci bit in scc1 ($0013); mmen and sdascl1 bits in mmcr1 ($0049) scl1 ptb3/scl1/rxd addr.register name bit 7654321bit 0 $0048 mmiic address register (mmadr) read: mmad7 mmad6 mmad5 mmad4 mmad3 mmad2 mmad1 mmextad write: reset:10100000 $0049 mmiic control register 1 (mmcr1) read: mmen mmien 00 mmtxak repsen mmcrcbyte sdascl1 write: mmclrbb reset:00000000 $004a mmiic control register 2 (mmcr2) read: mmalif mmnakif mmbb mmast mmrw 00 mmcrcef write: 0 0 reset:0000000 unaffected $004b mmiic status register (mmsr) read: mmrxif mmtxif mmatch mmsrw mmrxak mmcrcbf mmtxbe mmrxbf write: 0 0 reset:00001010 $004c mmiic data transmit register (mmdtr) read: mmtd7 mmtd6 mmtd5 mmtd4 mmtd3 mmtd2 mmtd1 mmtd0 write: reset:00000000 $004d mmiic data receive register (mddrr) read: mmrd7 mmrd6 mmrd5 mmr d4 mmrd3 mmrd2 mmrd1 mmrd0 write: reset:00000000 $004e mmiic crc data register (mmcrdr) read: mmcrcd7 mmcrcd6 mmcrcd5 mmcrcd4 mmcrcd3 mmcrcd2 mmcrcd1 mmcrcd0 write: reset:00000000 $004f mmiic frequency divider register (mmfdr) read: 00000 mmbr2 mmbr1 mmbr0 write: reset:00000100 = unimplemented figure 17-1. mmiic i/ o register summary
multi-master iic interface (mmiic) multi-master iic system configuration mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 295 17.5 multi-master ii c system configuration the multi-master iic system uses a serial data line sda and a serial clock line scl for data tr ansfer. all devices connec ted to it must have open collector (drain) outputs and the logical-and function is performed on both lines by two pull-up resistors. 17.6 multi-master iic bus protocol normally a standard communication is composed of four parts: 1. start signal, 2. slave address transmission, 3. data transfer, and 4. stop signal. these are described briefly in the fo llowing sections and illustrated in figure 17-2 . figure 17-2. multi-ma ster iic bus transmi ssion signal diagram 10 1 00011 1 0 1 10011 10 1 00011 1 0 1 10011 scl sda scl sda msb lsb msb lsb msb lsb msb lsb start stop repeated start stop 9th clock pulse 9th clock pulse ack no ack signal signal signal signal signal ack no ack start data must be stable when scl is high
multi-master iic interface (mmiic) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 296 multi-master iic interface (mmiic) freescale semiconductor 17.6.1 start signal when the bus is free, (i.e. no master device is engaging the bus ? both scl and sda lines are at logic high) a ma ster may initiate communication by sending a st art signal. as shown in figure 17-2 , a start signal is defined as a high to low transition of sda while scl is high. this signal denotes the beginning of a new data tr ansfer (each data transfer may contain several bytes of data) and wakes up all slaves. 17.6.2 slave address transmission the first byte transferred immediately after the start signal is the slave address transmitted by t he master. this is a 7-bit calling address followed by a r/w- bit. the r/w-bit dictates to the slave the desired direction of the data trans fer. a logic 0 indicates that the master wishes to transmit data to the sl ave; a logic 1 indicates that the master wishes to receive data from the slave. only the slave with a matched address will re spond by sending back an acknowledge bit by pulling sda low on the 9th clock cycle. (see figure 17-2 .) 17.6.3 data transfer once a successful slave addressing is achieved, the data transfer can proceed byte by byte in th e direction specified by the r/w-bit se nt by the calling master. each data byte is 8 bits. data c an be changed only when scl is low and must be held stable when scl is high as shown in figure 17-2 . the msb is transmitted first and each byte has to be followed by an acknowledge bit. this is signalled by the receiving device by pulling the sda low on the 9th clock cycle. ther efore, one complete data byte transfer requires 9 clock cycles. if the slave receiver does not a cknowledge the master, the sda line should be left high by the slave. the master can t hen generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new transfer.
multi-master iic interface (mmiic) multi-master iic bus protocol mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 297 if the master receiver does not ackn owledge the slave transmitter after a byte has been transmitted, it mean s an ?end of data? to the slave. the slave should release the sda line for the master to gen erate a stop or start signal. 17.6.4 repeated start signal as shown in figure 17-2 , a repeated start signal is used to generate start signal without first generat ing a stop to terminate the communication. this is us ed by the master to communicate with another slave or with the same slave in a di fferent mode (transmit/receive mode) without releas ing the bus. 17.6.5 stop signal the master can terminat e the communication by generating a stop signal to free the bus. however, the master may generate a start signal followed by a calling command without first g enerating a stop signal. this is called re peat start. a stop signal is defined as a low to high transition of sda while scl is at logic high (see figure 17-2 ). 17.6.6 arbitration procedure the interface circuit is a multi-mast er system which allows more than one master to be connected. if two or more masters try to control the bus at the same time, a cl ock synchronization proc edure determines the bus clock. the clock low period is equal to the longest clock low period and the clock high period is equal to the shortest one among the masters. a data arbitration procedure determines the priority . a master will lose arbitration if it transm its a logic 1 while another transmits a logic 0. the losing master will immediately swit ch over to slave receive mode and stops its data and clock out puts. the transition from master to slave will not generate a stop cond ition. meanwhile a soft ware bit will be set by hardware to indicates loss of arbitration.
multi-master iic interface (mmiic) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 298 multi-master iic interface (mmiic) freescale semiconductor 17.6.7 clock synchronization since wired-and logic is performed on scl line, a high to low transition on the scl line will affect the devices connected to the bus. the devices start counting their low period once a device?s clock has gone low, it will hold the scl line low until the clock hi gh state is reache d. however, the change of low to high in this device clock may not change the state of the scl line if another device clock is still in its low period. therefore the synchronized clock scl will be he ld low by the device which last releases scl to logic high. devices with shorter low periods enter a high wait state during this time. when all devices concerned have counted off their low period, the synchronized sc l line will be released and go high, and all devices will start counting t heir high periods. the first device to complete its high period will again pull the scl line low. figure 17-3 illustrates the clock syn chronization waveforms. figure 17-3. cl ock synchronization 17.6.8 handshaking the clock synchronization mechanism can be used as a handshake in data transfer. a slave de vice may hold the scl low after completion of one byte data transfer and will halt the bu s clock, forcing the master clock into a wait state until the slave releases the scl line. scl1 scl2 scl internal counter reset wait start counting high period
multi-master iic interface (mmiic) mmiic i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 299 17.6.9 packet error code the packet error code (pec) for the mm iic interface is in the form a cyclic redundancy code ( crc). the pec is gener ated by hardware for every transmitted and received byte of data. the tran smission of the generated pec is controlle d by user software. the crc data register, mmcrcdr, contains the gen erated pec byte, with three other bi ts in the mmiic control re gisters and status register monitoring and controll ing the pec byte. 17.7 mmiic i/o registers these i/o registers control and monitor mm iic operation: mmiic address regi ster (mmadr) ? $0048 mmiic control regist er 1 (mmcr1) ? $0049 mmiic control regist er 2 (mmcr2) ? $004a mmiic status register (mmsr) ? $004b mmiic data transmit register (mmdtr) ? $004c mmiic data receive r egister (mmdrr) ? $004d mmiic crc data regist er (mmcrcdr) ? $004e mmiic frequency divide r egister (mmfdr) ? $004f 17.7.1 mmiic address register (mmadr) address: $0048 bit 7654321bit 0 read: mmad7 mmad6 mmad5 mmad4 mmad3 mmad2 mmad1 mmextad write: reset:10100000 figure 17-4. mmiic addr ess register (mmadr)
multi-master iic interface (mmiic) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 300 multi-master iic interface (mmiic) freescale semiconductor mmad[7:1] ? multi-master address these seven bits represent the mmii c interface?s own specific slave address when in slave mode, and the calling address when in master mode. software must update mmad[7: 1] as the calling address while entering master mode and restore its own slave address after master mode is relinquished. thi s register is cleared as $a0 upon reset. mmextad ? multi-mast er expanded address this bit is set to ex pand the address of the mmiic in slave mode. when set, the mmiic wi ll acknowledge the foll owing addresses from a calling master: $mmad[7: 1], 0000000, and 0001100. reset clears this bit. 1 = mmiic responds to the following calling addresses: $mmad[7:1], 0000000, and 0001100. 0 = mmiic responds to address $mmad[7:1] for example, when mm adr is configured as: the mmiic module will res pond to the ca lling address: or the general calling address: or the calling address: note that bit-0 of t he 8-bit calling address is the mmrw bit from the calling master. mmad7 mmad6 mmad5 mmad4 mmad3 mmad2 mmad 1 mmextad 11010101 bit 765432bit 1 1101010 0000000 bit 765432bit 1 0001100
multi-master iic interface (mmiic) mmiic i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 301 17.7.2 mmiic control register 1 (mmcr1) mmen ? mmiic enable this bit is set to enable the multi-mast er iic module. when mmen = 0, module is disabled and all flags will restor e to its power- on default states. reset clears this bit. 1 = mmiic module enabled 0 = mmiic module disabled mmien ? mmiic interrupt enable when this bit is set, the mmtx if, mmrxif, mmalif, and mmnakif flags are enabled to generate an in terrupt request to the cpu. when mmien is cleared, the these flags are prevented from generating an interrupt request. re set clears this bit. 1 = mmtxif, mmrxif, mmalif, and/or mmnakif bit set will generate interrupt request to cpu 0 = mmtxif, mmrxif, mmalif, a nd/or mmnakif bit set will not generate interrupt request to cpu mmclrbb ? mmiic clear busy flag writing a logic 1 to this writ e-only bit clears the mmbb flag. mmclrbb always reads as a logi c 0. reset clears this bit. 1 = clear mmbb flag 0 = no affect on mmbb flag address: $0049 bit 7654321bit 0 read: mmen mmien 00 mmtxak repsen mmcrcbyte sdascl1 write: mmclrbb reset:00000000 = unimplemented figure 17-5. mmiic contro l register 1 (mmcr1)
multi-master iic interface (mmiic) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 302 multi-master iic interface (mmiic) freescale semiconductor mmtxak ? mmiic transmi t acknowledge enable this bit is set to disable the mmiic from sending out an acknowledge signal to the bus at the 9th clock bit after receiving 8 data bits. when mmtxak is cleared, an acknowledge signal wi ll be sent at the 9th clock bit. reset clears this bit. 1 = mmiic does not send ackno wledge signals at 9th clock bit 0 = mmiic sends acknowledge signal at 9th clock bit repsen ? repeated start enable this bit is set to enable repeated start signal to be generated when in master mode transfe r (mmast = 1). the repsen bit is cleared by hardware after the completion of repeated start signal or when the mmast bit is cleared. re set clears this bit. 1 = repeated start si gnal will be generated if mmast bit is set 0 = no repeated start si gnal will be generated mmcrcbyte ? mmiic crc byte in receive mode, this bit is set by software to indica te that the next receiving byte will be the packe t error checking (pec) data. in master receive mode, after co mpletion of crc generation on the received pec data, an a cknowledge signal is sent if mmtxak = 0; no acknowledge is sent if mmtxak = 1. in slave receive mode, no acknowl edge signal is sent if a crc error is detected on the received pec data. if no crc error is detected, an acknowledge signal is sent if mm txak = 0; no acknowledge is sent if mmtxak = 1. under normal operation, the user software should cl ear mmtxak bit before setting mmcrcbyte bit to ensure that an acknowledge signal is sent when no c rc error is detected. the mmcrcbyte bit should not be set in transmit mode. this bit is cleared by the next start signal. reset also clears this bit. 1 = next receiving byte is t he packet error checking (pec) data 0 = next receiving by te is not pec data
multi-master iic interface (mmiic) mmiic i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 303 sdascl1 ? sda and sc l i/o pin select this bit selects either sda0 and scl0, or s da1 and scl1, for mmiic i/o pins when mmiic module is enabled (mmen = 1). if the sci module is enabled (ensc i = 0), the sda1 and scl1 pins are not available for mmiic. reset clears sdascl1 bit. 1 = mmiic module uses sda1 and scl1 i/o pins 0 = mmiic module uses sda0 and scl0 i/o pins 17.7.3 mmiic control register 2 (mmcr2) mmalif ? arbitrati on loss interrupt flag this flag is set when software atte mpt to set mmast but the mmbb has been set by detecting the start condition on the lin es or when the mmiic is transmitting a "1" to sd a line but detecte d a "0" from sda line in master mode ? an arbitr ation loss. this bit generates an interrupt request to the cpu if th e mmien bit in mmcr1 is set. this bit is cleared by writing "0" to it or by reset. 1 = lost arbitrati on in master mode 0 = no arbitration lost mmnakif ? no acknowledge in terrupt flag (master mode) this flag is only set in master mo de (mmast = 1) when there is no acknowledge bit detected after one data byte or calling address is transferred. this flag also clear s mmast. mmnakif generates an interrupt request to cpu if the mmien bit in mmcr1 is se t. this bit is cleared by writing "0" to it or by reset. 1 = no acknowl edge bit detected 0 = acknowledg e bit detected address: $004a bit 7654321bit 0 read: mmalif mmnakif mmbb mmast mmrw 00 mmcrcef write: 0 0 reset:0000000 unaffected = unimplemented figure 17-6. mmiic contro l register 2 (mmcr2)
multi-master iic interface (mmiic) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 304 multi-master iic interface (mmiic) freescale semiconductor mmbb ? mmiic bus busy flag this flag is set after a start conditi on is detected (bus busy), and is cleared when a stop condition (bus idle) is detected or the mmiic is disabled. reset clears this bit. 1 = start condition detected 0 = stop condition detected or mmiic is disabled mmast ? mmiic master control this bit is set to initia te a master mode transf er. in master mode, the module generates a star t condition to the sda and scl lines, followed by sending the calli ng address stored in mmadr. when the mmast bit is cleared by mmnakif set (no acknowledge) or by software, the mo dule generates the stop condition to the lines after the current byte is transmitted. if an arbitration loss occurs (mmali f = 1), the module reverts to slave mode by clearing mmast, and releasing sda and scl lines immediately. this bit is cleared by writi ng "0" to it or by reset. 1 = master mode operation 0 = slave mode operation mmrw ? mmiic master read/write this bit is transmitted out as bit 0 of the ca lling address when the module sets the mmast bit to ent er master mode. the mmrw bit determines the transfer direction of the data bytes that follows. when it is "1", the module is in master receive mode. when it is "0", the module is in master transmit mode. reset clears this bit. 1 = master mode receive 0 = master mode transmit mmcrcef ? mmiic crc error flag this flag is set when a crc error is detected, and cleared when no crc error is detected. the mmcr cef is only meaningful after receiving a pec data. this flag is unaffected by reset. 1 = crc error detec ted on pec byte 0 = no crc error det ected on pec byte
multi-master iic interface (mmiic) mmiic i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 305 17.7.4 mmiic status register (mmsr) mmrxif ? mmiic rece ive interrupt flag this flag is set after the data receiv e register (mmdrr) is loaded with a new received data. once the mm drr is loaded with received data, no more received data can be loaded to the mmdrr register until the cpu reads the data from the mmdrr to clear mmrxbf flag. mmrxif generates an in terrupt request to cpu if the mmien bit in mmcr is also set. this bit is cleared by writing "0" to it or by reset; or when the mmen = 0. 1 = new data in data re ceive register (mmdrr) 0 = no data received mmtxif ? mmiic transmit interrupt flag this flag is set when data in the data transmit regi ster (mmdtr) is downloaded to the output circuit, and that new data ca n be written to the mmdtr. mmtxif generates an in terrupt request to cpu if the mmien bit in mmcr is also set. this bit is cleared by writing "0" to it or when the mmen = 0. 1 = data transfer completed 0 = data transfer in progress mmatch ? mmiic address match flag this flag is set when the received data in the data receive register (mmdrr) is a calling ad dress which matches wit h the address or its extended addresses (mmextad = 1) specified in the address register (mmadr). the mmatch flag is set at the 9th clock of the calling address and will be cleared on the 9th clock of the next receiving data. note: slave tr ansmits do not clear mmatch. address: $004b bit 7654321bit 0 read: mmrxif mmtxif mmatch mmsrw mmrxak mmcrcbf mmtxbe mmrxbf write: 0 0 reset:00001010 = unimplemented figure 17-7. mmiic st atus register (mmsr)
multi-master iic interface (mmiic) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 306 multi-master iic interface (mmiic) freescale semiconductor 1 = received address matches mmadr 0 = received address does not match mmsrw ? mmiic slave read/write select this bit indicates the data direction when the module is in slave mode. it is updated after t he calling address is rece ived from a master device. mmsrw = 1 when the calling ma ster is reading data from the module (slave transmit mode). mmsrw = 0 when the master is writing data to the m odule (receive mode). 1 = slave mode transmit 0 = slave mode receive mmrxak ? mmiic receive acknowledge when this bit is clear ed, it indicate s an acknowledge signal has been received after the comp letion of eight data bi ts transmission on the bus. when mmrxak is set, it indicates no acknowledge signal has been detected at the 9th clock; t he module will rel ease the sda line for the master to generate stop or repeated start condition. reset sets this bit. 1 = no acknowledge signal received at 9th clock 0 = acknowledge signal received at 9th clock mmcrcbf ? crc data buffer full flag this flag is set when the crc data register (mmcrcdr) is loaded with a crc byte for the curr ent received or transmitted data. in transmit mode, afte r a byte of data has been sent (mmtxif = 1), the mmcrcbf will be set when the crc byte has been generated and ready in the mmcrcdr. the c ontent of the mmcrcdr should be copied to the mm dtr for transmission. in receive mode, the mmcrcbf is set when the crc byte has been generated and ready in mmc rcdr, for the current byte of received data. the mmcrcbf bit is cleared when th e crc data regist er is read. reset also clears this bit. 1 = data ready in crc data register (mmcrcdr) 0 = data not ready in crc data regist er (mmcrcdr)
multi-master iic interface (mmiic) mmiic i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 307 mmtxbe ? mmiic trans mit buffer empty this flag indicates the status of th e data transmit r egister (mmdtr). when the cpu writes the data to the mmdtr, the mmtxbe flag will be cleared. mmtxbe is se t when mmdtr is empt ied by a transfer of its data to the out put circuit. reset sets this bit. 1 = data transmit register empty 0 = data transmit register full mmrxbf ? mmiic receive buffer full this flag indicates the status of th e data receive register (mmdrr). when the cpu reads the data from the mmdrr, the mmrxbf flag will be cleared. mmrx bf is set when mmdrr is full by a transfer of data from the input circ uit to the mmdrr. re set clears this bit. 1 = data receive register full 0 = data receive register empty 17.7.5 mmiic data transmit register (mmdtr) when the mmiic module is enabled, mmen = 1, data written into this register depends on whether module is in master or slave mode. in slave mode, the data in mmdtr will be transferr ed to the out put circuit when: the module detects a matched calling addres s (mmatch = 1), with the calling master requesting data (mmsrw = 1); or the previous data in the output circuit has be tr ansmitted and the receiving master returns an a cknowledge bit, indicated by a received acknowl edge bit (mmrxak = 0). address: $004c bit 7654321bit 0 read: mmtd7 mmtd6 mmtd5 mmtd4 mmtd3 mmtd2 mmtd1 mmtd0 write: reset:00000000 figure 17-8. mmiic data transmit register (mmdtr)
multi-master iic interface (mmiic) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 308 multi-master iic interface (mmiic) freescale semiconductor if the calling master does not re turn an acknowledge bit (mmrxak = 1), the module will release the sda line for master to generate a stop or repeated start condition. the da ta in the mmdt r will not be transferred to the output ci rcuit until the next ca lling from a master. the transmit buffer empty flag re mains cleared (mmtxbe = 0). in master mode, the dat a in mmdtr will be tr ansferred to the output circuit when: the module receives an acknow ledge bit (mmr xak = 0), after setting master transmit m ode (mmrw = 0), and the calling address has been transmitted; or the previous data in the output circuit has be tr ansmitted and the receiving slave retu rns an acknowledge bi t, indicated by a received acknowl edge bit (mmrxak = 0). if the slave does not return an acknowledge bit (mmrxak = 1), the master will generate a st op or repeated start condition. the data in the mmdtr will not be trans ferred to the output circuit. the transmit buffer empty flag remains cleared (mmtxbe = 0). the sequence of events for slave tr ansmit and master transmit are illustrated in figure 17-12 . 17.7.6 mmiic data r eceive register (mmdrr) when the mmiic module is enabled, mmen = 1, data in this read-only register depends on whether module is in master or slave mode. in slave mode, t he data in mmdrr is: address: $004d bit 7654321bit 0 read: mmrd7 mmrd6 mmrd5 mmrd4 mmrd3 mmrd2 mmrd1 mmrd0 write: reset:00000000 = unimplemented figure 17-9. mmiic data receive register (mmdrr)
multi-master iic interface (mmiic) mmiic i/o registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 309 the calling address from the ma ster when the address match flag is set (mmatch = 1); or the last data received when mmatch = 0. in master mode, the data in the mmdrr is: the last data received. when the mmdrr is read by the cpu, the receive buffer full flag is cleared (mmrxbf = 0), and the next re ceived data is loaded to the mmdrr. each time when new data is loaded to the mmdrr, the mmrxif interrupt flag is set, indicati ng that new data is available in mmdrr. the sequence of events for slave receive and master receive are illustrated in figure 17-12 . 17.7.7 mmiic crc data register (mmcrcdr) when the mmiic module is enabled, mmen = 1, and the crc buffer full flag is set (mmcrcbf = 1), data in this read-only register contains the generated crc byte for the last byte of receiv ed or transmitted data. a crc byte is generated for each rece ived and transmi tted data byte and loaded to the crc dat a register. the mmcrcbf bit will be set to indicate the crc byte is r eady in the crc data register. reading the crc data r egister clears the mmcrc bf bit. if the crc data register is not re ad, the mmcrcbf bit will be cleared by hardware before the next crc byte is loaded. address: $004e bit 7654321bit 0 read: mmcrcd7 mmcrcd6 mmcrcd5 mmcrcd4 mmcrcd3 mmcrcd2 mmcrcd1 mmcrcd0 write: reset:00000000 = unimplemented figure 17-10. mmiic crc da ta register (mmcrcdr)
multi-master iic interface (mmiic) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 310 multi-master iic interface (mmiic) freescale semiconductor 17.7.8 mmiic frequency di vider regist er (mmfdr) the three bits in the frequency divi der register (mmfdr) selects the divider to divide the bus clock to the desired baud rate for the mmiic data transfer. table 17-2 shows the divider va lues for mmbr[2:0]. note: the frequency of the mmiic baud rate is only guaranteed for 100khz to 10khz. the divider is available for the flexibility on bus frequency selection. address: $004f bit 7654321bit 0 read: 00000 mmbr2 mmbr1 mmbr0 write: reset:00000100 = unimplemented figure 17-11. mmiic frequency divider register (mmfdr) table 17-2. mmiic baud rate selection mmbr2 mmbr1 mmbr0 divider mmiic baud rates for bus clocks: 8mhz 4mhz 2mhz 1mhz 0 0 0 20 400khz 200khz 100khz 50khz 0 0 1 40 200khz 100khz 50khz 25khz 0 1 0 80 100khz 50khz 25khz 12.5khz 0 1 1 160 50khz 25khz 12.5khz 6.25khz 1 0 0 320 25khz 12.5khz 6.25khz 3.125khz 1 0 1 640 12.5khz 6.25khz 3.125khz 1.5625khz 1 1 0 1280 6.25khz 3.125khz 1.5625khz 0.78125khz 1 1 1 2560 3.125khz 1.5625khz 0.78125khz 0.3906khz
multi-master iic interface (mmiic) program algorithm mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 311 17.8 program algorithm when the mmiic module detects an arbi tration loss in ma ster mode, it releases both sda and scl lines immediately. but if there are no further stop conditions detected, the module will hang up. therefore, it is recommended to have time-o ut software to recove r from this condition. the software can start the time-out counter by looking at the mmbb (bus busy) flag and reset the counter on the completion of one byte transmission. if a time-out has occu rred, software ca n clear the mmen bit (disable mmiic module) to re lease the bus, and hence clear the mmbb flag. this is the only way to clear the mmbb flag by software if the module hangs up due to a no stop condition received. the mmiic can resume operation again by setting the mmen bit.
multi-master iic interface (mmiic) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 312 multi-master iic interface (mmiic) freescale semiconductor 17.8.1 data sequence figure 17-12. data transfer sequences fo r master/slave transmit/receive modes start address ack tx data1 mmtxbe=0 mmrw=0 mmast=1 mmtxif=1 mmtxbe=1 mmnakif=1 mmast=0 mmtxbe=1 (a) master transmit mode (b) master receive mode (c) slave transmit mode mmtxif=1 mmtxbe=0 ack tx datan ack stop mmtxif=1 mmtxbe=1 start address ack rx data1 mmrxbf=0 mmast=1 mmtxbe=0 mmrxbf=1 mmrxif=1 mmnakif=1 mmast=0 mmrxif=1 mmrxbf=1 ack rx datan nak stop 1 start address ack tx data1 mmtxbe=1 mmrxbf=0 mmnakif=1 mmtxbe=0 mmtxbe=1 (d) slave receive mode mmtxif=1 ack tx datan nak stop mmrxbf=1 mmrxif=1 mmatch=1 mmsrw=1 mmtxif=1 mmtxbe=1 0 start address ack rx data1 mmrxbf=1 mmrxif=1 mmrxif=1 mmrxbf=1 ack rx datan ack stop mmtxbe=0 mmrxbf=0 mmrxbf=1 mmrxif=1 mmatch=1 mmsrw=0 data1 mmdrr datan mmdrr data1 mmdtr data2 mmdtr datan+2 mmdtr data1 mmdtr data2 mmdtr data3 mmdtr datan+2 mmdtr (dummy data mmdtr) mmrw=1 data1 mmdrr datan mmdrr 0 1 shaded data packets indicate transmissions by the mcu
multi-master iic interface (mmiic) smbus protocols with pec and without pec mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 313 17.9 smbus protocols with pec and without pec following is a descriptio n of the various mmiic bus protocols with and without a packet error code (pec). 17.9.1 quick command figure 17-13. quick command 17.9.2 send byte figure 17-14. send byte 17.9.3 receive byte figure 17-15. receive byte start slave address ack stop rw master to slave slave to master command bit acknowledge stop condition start condition 17111 start slave address ack w command code ack stop ack stop pec start slave address ack w command code ack (a) send byte protocol (b) send byte protocol with pec start slave address ack r data byte nak stop nak stop pec start slave address ack r data byte ack (b) receive byte protocol with pec (a) receive byte protocol
multi-master iic interface (mmiic) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 314 multi-master iic interface (mmiic) freescale semiconductor 17.9.4 write byte/word figure 17-16. write byte/word 17.9.5 read byte/word figure 17-17. read byte/word ack command code ack data byte low ack data byte high ack stop ack command code ack data byte ack stop ack stop pec start slave address w start slave address w ack command code ack data byte ack start slave address w (a) write byte protocol (b) write byte protocol with pec (c) write word protocol ack command code ack data byte low ack data byte high ack ack stop pec start slave address w (d) write word protocol with pec stop ack command code ack data byte low ack data byte high pec data byte high ack nak ack nak start ack command code ack data byte low ack ack start stop start slave address w start slave address w slave address r slave address r (d) read word protocol with pec (c) read word protocol (b) read byte protocol with pec ack command code ack data byte nak ack command code ack nak stop pec ack start ack data byte ack start start slave address w start slave address w slave address r slave address r stop (a) read byte protocol
multi-master iic interface (mmiic) smbus protocols with pec and without pec mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 315 17.9.6 process call figure 17-18. process call 17.9.7 block read/write figure 17-19. bl ock read/write nak stop ack command code data byte low ack ack data byte high ack data byte low data byte high ack nak ack stop pec start slave address w start slave address r ack command code data byte low ack ack data byte high ack data byte low data byte high ack ack ack stop start slave address w start slave address r (b) process call with pec (a) process call ack command code ack byte count = n ack data byte 1 ack data byte 2 ack data byte n nak stop start ack ack command code ack byte count = n ack data byte 1 ack data byte 2 ack data byte n ack stop start slave address w start slave address w slave address r data byte 1 ack command code ack byte count = n ack ack data byte 2 ack data byte n nak stop start ack start slave address w slave address r data byte 1 pec ack (d) block write with pec (c) block write (b) block read with pec ack command code ack byte count = n ack data byte 1 ack data byte 2 ack data byte n ack stop start slave address w pec ack (a) block read
multi-master iic interface (mmiic) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 316 multi-master iic interface (mmiic) freescale semiconductor 17.10 smbus protocol implementation figure 17-20. smbus pr otocol implementation start address ack command ack 0 start ack stop rx data1 ack nak rx datan address 1 ack prepare for master mode action: 1. load slave address to mmadr 2. clear mmrw 3. load command to mmdtr 4. set mmast operation: prepare for repeated start flags: mmtxif set mmrxak clear operation: action: 1. set mmrw 2. set repsen 3. clear mmtxak 4. load dummy ($ff) to mmdtr get ready to receive data flags: mmtxif set mmrxak clear operation: action: load dummy ($ff) to mmdtr generate stop flags: mmrxif set operation: action: read datan from mmdrr read received data and prepare for stop flags: mmrxif set operation: action: 1. set mmtxak 2. read data(n-1) from mmdrr 3. clear mmast read received data flags: mmrxif set operation: action: read data1 from mmdrr master mode start address ack command ack 0 start ack stop tx data1 ack nak tx datan address 1 ack slave address match and flags: mmrxif set mmatch set operation: action: 1. check mmsrw 2. read slave address read and decode received command flags: mmrxif set mmatch clear operation: action: load data1 to mmdtr last data sent flags: mmtxif set mmrxak set operation: action: load dummy ($ff) to mmdtr last data is going to be sent flags: mmtxif set operation: action: load dummy ($ff) to mmdtr transmit data flags: mmtxif set operation: action: load data3 to mmdtr prepare for slave mode action: 1. load slave address to mmadr 2. clear mmtxak 3. clear mmast operation: mmsrw depends on 8th slave address match and flags: mmrxif set mmatch set operation: action: check mmsrw mmsrw depends on 8th mmrxak clear mmrxak clear transmit data flags: mmtxif set operation: action: load data2 to mmdtr check for data direction bit of calling address byte get ready to transmit data bit of calling address byte slave mode shaded data packets indicate transmissions by the mcu
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor input/output (i/o) ports 317 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 18. input/output (i/o) ports 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 18.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 18.3.1 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . 320 18.3.2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 321 18.3.3 port a led control register (leda ) . . . . . . . . . . . . . . . . . 323 18.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 18.4.1 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . 324 18.4.2 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 325 18.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 18.5.1 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . 327 18.5.2 data direction register c (ddrc). . . . . . . . . . . . . . . . . . . 329 18.5.3 port c led control register (ledc ) . . . . . . . . . . . . . . . . . 330 18.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 18.6.1 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . 331 18.6.2 data direction register d (ddrd). . . . . . . . . . . . . . . . . . . 332 18.2 introduction thirty-one (31) bidirecti onal input-output (i/o) pins form four parallel ports. all i/o pins are progr ammable as inputs or outputs. note: connect any unused i/o pins to an appr opriate logic level, either v dd or v ss . although the i/o port s do not require te rmination for proper operation, termination reduces e xcess current consumption and the possibility of el ectrostatic damage.
input/output (i/o) ports data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 318 input/output (i/o) ports freescale semiconductor addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: 0 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: ptc7 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: 0 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $000c port-a led control register (leda) read: 0 0 leda5 leda4 leda3 leda2 leda1 leda0 write: reset:00000000 $000d port-c led control register (ledc) read: ledc7 ledc6 ledc5 ledc4 ledc3 000 write: reset:00000000 figure 18-1. i/o port register summary
input/output (i/o) ports introduction mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor input/output (i/o) ports 319 table 18-1. port contro l register bits summary port bit ddr module control pin module register control bit a 0 ddra0 adc adscr ($0057) adch[4:0] pta0/atd2 1 ddra1 pta1/atd3 2 ddra2 pta2/atd4 3 ddra3 pta3/atd5 4 ddra4 pta4/atd6 5 ddra5 pta5/atd7 6 ddra6 tim1 t1sc0 ($0025) els0b:els0a pta6/t1ch0 7 ddra7 t1sc1 ($0028) el s1b:els1a pta7/t1ch1 b 0 ddrb0 mbus mmcr1 ($0049) mmen sdascl1 ptb0/sda0 (1) 1 ddrb1 ptb1/scl0 (1) 2 ddrb2 sci scc1 ($0013) (2) ensci ptb2/sda1/txd (1) 3 ddrb3 mbus mmcr1 ($0049) mmen sdascl1 ptb3/scl1/rxd (1) 4 ddrb4 tim2 t2sc0 ($0030) els0b:els0a ptb4/t2ch0 5 ddrb5 t2sc1 ($0033) el s1b:els1a ptb5/t2ch1 6 ddrb6 irq ? ? ptb6/irq2 c 0 ddrc0 analog config2 ($001d) (1) cdoen ptc0/pwm0/cd pwm pwmcr ($0051) pch0 1 ddrc1 pch1 ptc1/pwm1 2 ddrc2 pch2 ptc2/pwm2 3 ddrc3 adc adscr ($0057) adch[4:0] ptc3/atd8 4 ddrc4 ptc4/atd9 5 ddrc5 ptc5/atd10 6 ddrc6 ptc6/atd11 7 ddrc7 ptc7/atd12 d 0 ddrd0 kbi kbier ($001b) kbie0 ptd0/kbi0 1 ddrd1 kbie1 ptd1/kbi1 2 ddrd2 kbie2 ptd2/kbi2 3 ddrd3 kbie3 ptd3/kbi3 4 ddrd4 kbie4 ptd4/kbi4 5 ddrd5 kbie5 ptd5/kbi5 6 ddrd6 kbie6 ptd6/kbi6 7 ddrd7 kbie7 ptd7/kbi7 notes : 1. pins are open-drain when configured as outputs. pullup resistors must be connected when configured as outputs. 2. register has the highest priority control on port pin.
input/output (i/o) ports data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 320 input/output (i/o) ports freescale semiconductor 18.3 port a port a is an 8-bit special function port that shares six of its port pins with the analog-to-digital conver ter (adc) module and tw o of its port pins with the timer interface module 1 (tim1). see section 15. analog-to-digital converter (adc) and section 11. timer in terface module (tim) . pta5?pta0 pins can be confi gured for direct led drive. 18.3.1 port a data register (pta) the port a data register co ntains a data latch for each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. atd[7:2] ? adc channels 2 to 7 atd[7:2] are pins used for the input channels to the analog-to-digital converter module. the channel sele ct bits, adch[4:0], in the adc status and control regi ster define which port pin will be used as an adc input and overrides any control from t he port i/o logic. see section 14. analog module . address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset alternative function: t1ch1 t1ch0 atd7 atd6 atd5 atd4 atd3 atd2 additional function: led drive led drive led drive led drive led drive led drive figure 18-2. port a data register (pta)
input/output (i/o) ports port a mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor input/output (i/o) ports 321 t1ch[1:0] ? timer 1 channel i/o bits the t1ch1 and t1ch0 pins are the tim1 input c apture/output compare pins. the edge/leve l select bits, elsx b:elsxa, determine whether the pta7/t1ch1 and pta6/t1ch0 pi ns are timer channel i/o pins or general- purpose i/o pins. see section 11. timer interface module (tim) . note: care must be taken when reading port a while applyin g analog voltages to atd[7:2] pins. if the appropriate adc channel is not enabled, excessive current drain may occur if analog voltages are applied to the ptax/atdx pin, while pt a is read as a digita l input. those ports not selected as analog input channels are considered digital i/o ports. led drive ? direct led drive pins pta5?pta0 pins can be configur ed for direct led drive. see 18.3.3 port a led contro l register (leda) . 18.3.2 data directio n register a (ddra) data direction register a determine s whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables t he output buffer for the corresponding port a pin; a logi c 0 disables the output buffer. ddra[7:0] ? data dire ction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 18-3. data dir ection register a (ddra)
input/output (i/o) ports data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 322 input/output (i/o) ports freescale semiconductor note: avoid glitches on port a pi ns by writing to the port a data register before changing data direction register a bits from 0 to 1. figure 18-4 shows the port a i/o logic. figure 18-4. port a i/o circuit when ddrax is a logic 1, readi ng address $0000 reads the ptax data latch. when ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data la tch can always be written, regardless of the state of its data direction bit. table 18-2 summarizes the operat ion of the port a pins. table 18-2. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddra[7:0] pin pta[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddra[7:0] pta[7:0] pta[7:0] read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus
input/output (i/o) ports port b mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor input/output (i/o) ports 323 18.3.3 port a led c ontrol register (leda) the port-a led control register (leda) controls the di rect led drive capability on pta5?pta0 pins. each bi t is individually configurable and requires that the data di rection register, ddra, bit be configured as an output. leda[5:0] ? port a led drive enable bits these read/write bits are software programmable to enable the direct led drive on an output port pin. 1 = corresponding port a pin conf igured for dire ct led drive 0 = corresponding port a pin configured for standard drive 18.4 port b port b is a 7-bit special function port t hat shares four of its port pins with the multi-master iic (mmii c) interface module, two of its port pins with the serial communication s interface (sci) module, two of its port pins with the timer interface module 2 (tim2) , and one of its por t pins with the irq module. see section 17. multi-master iic interface (mmiic) , section 16. serial comm unications in terface (sci) , section 11. timer interface module (tim) , and section 19. external interrupt (irq) . note: ptb3?ptb0 are open-drai n pins when configured as outputs regardless whether the pins are us ed as general purpose i/ o pins, mmiic pins, or sci pins. therefore, when configured as general purpose output pins, mmiic pins, or sci pins (the tx d pin), pullup resistors must be connected to these pins. address: $000c bit 7654321bit 0 read: 0 0 leda5 leda4 leda3 leda2 leda1 leda0 write: reset:00000000 figure 18-5. port a led control register (leda)
input/output (i/o) ports data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 324 input/output (i/o) ports freescale semiconductor 18.4.1 port b data register (ptb) the port b data register co ntains a data latch for each of the eight port b pins. ptb[6:0] ? port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. sda0, scl0, sda1, scl1 ? mmiic channels 1 and 2 sdax and sclx are the data and cl ock lines for the mmiic module. the multi-master enable bit, mmen, and the mmiic channel select bit, sdascl1, in the mmiic control register 1 determine whether the ptb0/sda0, ptb1/sc l0, ptb2/sda1/txd, and ptb3/scl1/rxd pins are mmiic i/o pins or general purpose i/o pins. see section 17. multi-master iic interface (mmiic) . txd, rxd ? sci data i/o pins the txd and rxd pins are the transmi t data output and receive data input for the sci module. the enable sci bit, ensci, in the sci control register 1 enables the ptb2/sda1/t xd and ptb3/scl1/rxd pins as sci txd and rxd pins and ov errides any contro l from the port i/o or mmiic logic. see section 16. serial communications interface (sci) . address: $0001 bit 7654321bit 0 read: 0 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternative functions: irq2 t2ch1 t2ch0 rxd txd scl0 sda0 scl1 sda1 these four pins are open-drain when configured as output pins. pullup resistors must be connected when configured as outputs. figure 18-6. port b data register (ptb)
input/output (i/o) ports port b mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor input/output (i/o) ports 325 t2ch[1:0] ? timer 2 channel i/o bits the t2ch1 and t2ch0 pins are the tim2 input c apture/output compare pins. the edge/leve l select bits, elsx b:elsxa, determine whether the ptb5/t2ch1 and ptb4/t2ch0 pi ns are timer channel i/o pins or general- purpose i/o pins.see section 11. timer interface module (tim) . irq2 ? external interrupt pin 2 irq2 pin is the second ex ternal interrupt input to the irq module. when ptb6/irq2 is configured as an input by the data direction bit bit, ddrb6, the pin is bo th a standard port inpu t pin and an external interrupt pin. see section 19. exter nal interrupt (irq) . 18.4.2 data directio n register b (ddrb) data direction register b determine s whether each port b pin is an input or an output. writing a logic 1 to a ddrb bit enables t he output buffer for the corresponding port b pin; a logi c 0 disables the output buffer. table 18-3. ptb2 and ptb3 pin configurations pin ensci bit ($0013) mmen bit ($0049) sdascl1 bit ($0049) pin function ptb2/sda1/txd ptb3/scl1/rxd 00x ptb2, ptb3 0 1 0 ptb2, ptb3 0 1 1 sda1, scl1 1 x x txd, rxd address: $0005 bit 7654321bit 0 read: 0 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 18-7. data dir ection register b (ddrb)
input/output (i/o) ports data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 326 input/output (i/o) ports freescale semiconductor ddrb[6:0] ? data dire ction register b bits these read/write bits control port b data direction. reset clears ddrb[6:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pi ns by writing to the port b data register before changing data direction register b bits from 0 to 1. figure 18-8 shows the port b i/o logic. figure 18-8. port b i/o circuit when ddrbx is a logic 1, readi ng address $0001 reads the ptbx data latch. when ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data la tch can always be written, regardless of the state of its data direction bit. table 18-4 summarizes the operat ion of the port b pins. table 18-4. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrb[6:0] pin ptb[6:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrb[6:0] ptb[6:0] ptb[6:0] read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx # ddrbx ptbx internal data bus # ptb3?ptb0 are open-drain pins when configured as outputs.
input/output (i/o) ports port c mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor input/output (i/o) ports 327 18.5 port c port c is an 8-bit special function port that shares thr ee of its port pins with the pulse width modulator module, five of its por t pins with the analog-to-digital converter module, and one of its pins with the analog module. see section 13. pulse width modulator (pwm) , section 15. analog-to-digital converter (adc) , and section 14. analog module . ptc7?ptc3 pins can be confi gured for direct led drive. 18.5.1 port c data register (ptc) the port c data regist er contains a data latch fo r each of t he six port c pins. note: bit 7 and bit 6 of ptc ar e not available in a 42-pi n shrink dual in-line package. ptc[7:0] ? port c data bits these read/write bits are software programmable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. address: $0002 bit 7654321bit 0 read: ptc7 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset alternative function: atd12 atd11 atd10 atd9 atd8 pwm2 pwm1 pwm0 cd additional function: led drive led drive led drive led drive led drive figure 18-9. port c data register (ptc)
input/output (i/o) ports data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 328 input/output (i/o) ports freescale semiconductor pwm[2:0] ? pwm channels 0 to 2 pwm[2:0] are pins used for the output channel s from the pulse width modulator (pwm) module. the pwm enables bit, pch[2:0], in the pwm control regist er define which port pin w ill be used as a pwm output and overrides any control fr om the port i/o lo gic. the pwm0 function on pct0/pwm0/cd pin can be overrided by the cd output function. see section 13. pulse wi dth modulator (pwm) . atd[12:8] ? adc channels 8 to 12 atd[12:8] are pins used for the inpu t channels to the analog-to-digital converter module. the channel sele ct bits, adch[4:0], in the adc status and control regi ster define which port pin will be used as an adc input and overrides any control from t he port i/o logic. see section 15. analog-to-dig ital converter (adc) . note: care must be taken w hen reading port c while applying analog voltages to atd[12:8] pins. if the appropr iate adc channel is not enabled, excessive current drain may occur if analog voltages are applied to the ptcx/atdx pin, while pt c is read as a digita l input. those ports not selected as analog input channels are considered digital i/o ports. cd ? current detect output pin the cd pin is used fo r the current detect ou tput from the analog module. the pin reflects the status of the current detect interrupt flag. the current detect output enable bit, cdoen, in the configuration register 2 enables the ptc0/pwm0/ cd pin as the cd output pin and overrides any control from the port i/o or pwm logic. see section 14. analog module . led drive ? direct led drive pins ptc7?ptc3 pins can be configur ed for direct led drive. see 18.5.3 port c led contro l register (ledc) . table 18-5. ptc0 pin configuration pin cdoen bit ($001d) pch0 bit ($0051) pin function ptc0/pwm0/cd 00 ptc0 01 pwm0 1x cd
input/output (i/o) ports port c mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor input/output (i/o) ports 329 18.5.2 data directio n register c (ddrc) data direction register c determines whether eac h port c pin is an input or an output. writing a logic 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a logi c 0 disables the output buffer. ddrc[7:0] ? data dire ction register c bits these read/write bits control port c data direction. reset clears ddrc[7:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writ ing to the port c dat a register before changing data direction register c bits from 0 to 1. figure 18-11 shows the port c i/o logic. note: for those devices packaged in a 42- pin shrink dual in-line package, ptc6 and ptc7 are not connected. ddrc6 and ddrc7 should be set to a 1 to configure ptc6 and ptc7 as outputs. figure 18-11. port c i/o circuit address: $0006 bit 7654321bit 0 read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 figure 18-10. data dir ection register b (ddrb) read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus
input/output (i/o) ports data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 330 input/output (i/o) ports freescale semiconductor when ddrcx is a logic 1, reading address $0002 reads the ptcx data latch. when ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data la tch can always be written, regardless of the state of its data direction bit. table 18-6 summarizes the operat ion of the port c pins. 18.5.3 port c led c ontrol register (ledc) the port-c led control register (ledc) controls the di rect led drive capability on ptc7?ptc3 pi ns. each bit is indi vidually configurable and requires that the data di rection register, ddrd, bit be configured as an output. ledc[7:3] ? port c led drive enable bits these read/write bits are software programmable to enable the direct led drive on an output port pin. 1 = corresponding port c pin conf igured for dire ct led drive 0 = corresponding port c pin configured for standard drive table 18-6. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrc[7:0] pin ptc[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrc[7:0] ptc[7:0] ptc[7:0] address: $000d bit 7654321bit 0 read: ledc7 ledc6 ledc5 ledc4 ledc3 000 write: reset:00000000 figure 18-12. port a led control register (leda)
input/output (i/o) ports port d mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor input/output (i/o) ports 331 18.6 port d port d is an 8-bit special function port that shares all of its pins with the keyboard interrupt module. see section 20. keyboard interrupt module (kbi) . 18.6.1 port d data register (ptd) the port d data register c ontains a data latch for each of the eight port d pins. ptd[7:0] ? port d data bits these read/write bits are software programmable. data direction of each port d pin is under the control of the corresponding bit in data direction register d. reset has no effect on port d data. kbi[7:0] ? keyboard interrupt pins the keyboard interrupt enable bits , kbie[7:0], in the keyboard interrupt enable register (kbier), enable the port d pins as external interrupt pins. see section 20. keyboard in terrupt module (kbi) . address: $0003 bit 7654321bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset alternative function: kbi7 kbi6 kbi5 kbi4 kbi3 kbi2 kbi1 kbi0 figure 18-13. port d data register (ptd)
input/output (i/o) ports data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 332 input/output (i/o) ports freescale semiconductor 18.6.2 data directio n register d (ddrd) data direction register d determines whether eac h port d pin is an input or an output. writing a logic 1 to a ddrd bit enables the output buffer for the corresponding port d pin; a logi c 0 disables the output buffer. ddrd[7:0] ? data dire ction register d bits these read/write bits control port d data direction. reset clears ddrd[7:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note: avoid glitches on port d pins by writ ing to the port d dat a register before changing data direction register d bits from 0 to 1. figure 18-15 shows the port d i/o logic. figure 18-15. port d i/o circuit address: $0007 bit 7654321bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 18-14. data dir ection register d (ddrd) read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus
input/output (i/o) ports port d mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor input/output (i/o) ports 333 when ddrdx is a logic 1, reading address $0003 reads the ptdx data latch. when ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data la tch can always be written, regardless of the state of its data direction bit. table 18-7 summarizes the operat ion of the port d pins. table 18-7. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrd[7:0] pin ptd[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrd[7:0] ptd[7:0] ptd[7:0]
input/output (i/o) ports data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 334 input/output (i/o) ports freescale semiconductor
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor external interrupt (irq) 335 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 19. external interrupt (irq) 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 19.5 irq1 and irq2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 19.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 339 19.7 irq registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 19.7.1 irq1 status an d control register . . . . . . . . . . . . . . . . . . . 340 19.7.2 irq2 status an d control register . . . . . . . . . . . . . . . . . . . 341 19.2 introduction the external interrupt (irq) module provides two maskable interrupt inputs: irq1 and irq2. 19.3 features features of the irq module include: a dedicated external interrupt pin, irq1 an external interrupt pin s hared with a port pin, irq2 /ptb6 separate irq interrupt control bits for irq1 and irq2 hysteresis buffers programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge internal pullup resistor, wi th disable option on irq2
external interrupt (irq) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 336 external interrupt (irq) freescale semiconductor note: references to either irq1 or irq2 may be made in the following text by omitting the irq number. for example, irqf may refer generically to irq1f and irq2f, and imask ma y refer to im ask1 and imask2. 19.4 functional description a logic 0 applied to the ex ternal interrupt pin ca n latch a cpu interrupt request. figure 19-2 and figure 19-3 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until on e of the following actions occurs: vector fetch ? a vector fetch au tomatically generates an interrupt acknowledge signal that clears t he latch that caused the vector fetch. software clear ? software can clear an interrupt latch by writing to the appropriate ackn owledge bit in the in terrupt status and control register (intscr). writing a logic 1 to the ack bit clears the irq latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is fal ling-edge-triggered and is software- configurable to be either falli ng-edge or falling-edge and low-level- triggered. the mode bit in the intscr controls the triggering sensitivity of the irq pin. addr.register name bit 7654321bit 0 $001c irq2 status and control register (intscr2) read: 0 ptbpue6 00irq2f0 imask2 mode2 write: ack2 reset:00000000 $001e irq1 status and control register (intscr1) read: 0000irq1f0 imask1 mode1 write: ack1 reset:00000000 = unimplemented figure 19-1. external interr upt i/o register summary
external interrupt (irq) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor external interrupt (irq) 337 when an interrupt pin is edge-triggered only, the interrupt remains set until a vector fetch, softwa re clear, or reset occurs. when an interrupt pin is both falli ng-edge and low-level-triggered, the interrupt remains set until both of the following occur: vector fetch or software clear return of the interr upt pin to logic 1 the vector fetch or software clear ma y occur before or af ter the interrupt pin returns to logic 1. as long as the pin is low, t he interrupt request remains pending. a reset will clear th e latch and the mode1 control bit, thereby clearing the interrup t even if the pin stays low. when set, the imask bit in the intscr mask a ll external interrupt requests. a latched interrupt request is not pres ented to the interrupt priority logic unless t he imask bit is clear. note: the interrupt mask (i) in the conditi on code register (ccr) masks all interrupt requests, including external interrupt requests. figure 19-2. irq1 block diagram ack1 imask1 dq ck clr irq1 high interrupt to mode select logic irq1 ff request v dd mode1 voltage detect synchro- nizer irq1f to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd internal pullup device irq1
external interrupt (irq) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 338 external interrupt (irq) freescale semiconductor figure 19-3. irq2 block diagram 19.5 irq1 and irq2 pins a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear , or reset clears the irq latch. if the mode bit is set, the irq pin is both falling- edge-sensitive and low- level-sensitive. with mode set, both of the following actions must occur to clear irq: vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to cl ear the latch. software may generate the interrupt acknowledge si gnal by writing a logic 1 to the ack bit in the interrupt stat us and control register (intscr). the ack bit is useful in appl ications that poll the irq pin and require software to clear the irq la tch. writing to the ack bit prior to leaving an interrupt service r outine can also prevent spurious interrupts due to noise. setting ack does not af fect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bit another interrupt request. if the irq mask bit, imask, is clear, t he cpu loads the program counter with the vector address at location defined in table 2-1 . vector addresses . ack2 imask2 dq ck clr irq2 interrupt irq2 ff request v dd mode2 synchro- nizer irq2f vector fetch decoder internal address bus reset v dd internal pullup device irq2 ptbpue6
external interrupt (irq) irq module during break interrupts mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor external interrupt (irq) 339 return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, irq remains active. the vector fetch or software cl ear and the retu rn of the irq pin to logic 1 may occur in any order. the interrupt request rema ins pending as long as the irq pin is at logic 0. a reset will clear the latch and the mode control bit, thereby cl earing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge- sensitive only. with mode clear, a vector fetc h or software clear im mediately clears the irq latch. the irqf bit in the intscr register can be used to check for pending interrupts. the irqf bit is not affect ed by the imask bit, which makes it useful in applications wh ere polling is preferred. use the bih or bil in struction to read the logic level on the irq1 pin. note: the bih and bil instructions do not re ad the logic level on the irq2 pin. note: when using the level-sensit ive interrupt trigger, av oid false interrupts by masking interrupt requests in the interrupt routine. the irq1 pin has a permanent internal pullup device connected, while the irq2 pin has an optional pullup device that can be enabled or disabled by the ptbpue6 bit in the intscr2 register. 19.6 irq module du ring break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear the latch during the break state. (see section 23. break module (brk) .) to allow software to clear the irq la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared dur ing the break state, it remains cleared when the m cu exits the break state. to protect cpu interrupt fl ags during the break stat e, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), writing to the ack bit in the irq status and control regi ster during the br eak state has no effect on the ir q interrupt flags.
external interrupt (irq) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 340 external interrupt (irq) freescale semiconductor 19.7 irq registers each irq is controlled and monitored by an status and control register. irq1 status and cont rol register ? $001e irq2 status and cont rol register ? $001c 19.7.1 irq1 status and control register the irq1 status and control register (intscr1) controls and monitors operation of irq1. the intscr1 has the following functions: shows the state of the irq1 flag clears the irq1 latch masks irq1 interrupt request controls triggering se nsitivity of the irq1 interrupt pin irq1f ? irq1 flag bit this read-only status bi t is high when the irq1 interrupt is pending. 1 = irq1 interrupt pending 0 = irq1 interrupt not pending ack1 ? irq1 interrupt request acknowledge bit writing a logic 1 to th is write-only bit clears the irq1 latch. ack1 always reads as logic 0. reset clears ack1. address: $001e bit 7654321bit 0 read: 0000irq1f0 imask1 mode1 write: ack1 reset:00000000 = unimplemented figure 19-4. irq1 status and control register (intscr1)
external interrupt (irq) irq registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor external interrupt (irq) 341 imask1 ? irq1 interrupt mask bit writing a logic 1 to this read/write bit disables irq1 interrupt requests. reset clears imask1. 1 = irq1 interrupt requests disabled 0 = irq1 interrupt requests enabled mode1 ? irq1 edge/level select bit this read/write bit cont rols the triggering se nsitivity of the irq1 pin. reset clears mode1. 1 = irq1 interrupt requests on falling edges and low levels 0 = irq1 interrupt requests on falling edges only 19.7.2 irq2 status and control register the irq2 status and control register (intscr2) controls and monitors operation of irq2. the intscr2 has the following functions: enables/disables the inte rnal pullup device on irq2 pin shows the state of the irq2 flag clears the irq2 latch masks irq2 interrupt request controls triggering se nsitivity of the irq2 interrupt pin ptbpue6 ? irq2 pin pullup enable bit. setting this bit to logic 1 di sables the pull up on ptb6/irq2 pin. reset clears this bit. 1 = irq2 pin internal pu ll-up is disabled 0 = irq2 pin internal pull-up is enabled address: $001c bit 7654321bit 0 read: 0 ptbpue6 00irq2f0 imask2 mode2 write: ack2 reset:00000000 = unimplemented figure 19-5. irq2 status and control register (intscr2)
external interrupt (irq) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 342 external interrupt (irq) freescale semiconductor irq2f ? irq2 flag bit this read-only status bi t is high when the irq2 interrupt is pending. 1 = irq2 interrupt pending 0 = irq2 interrupt not pending ack2 ? irq2 interrupt request acknowledge bit writing a logic 1 to th is write-only bit clears the irq2 latch. ack2 always reads as logic 0. reset clears ack2. imask2 ? irq2 interrupt mask bit writing a logic 1 to this read/write bit disables irq2 interrupt requests. reset clears imask2. 1 = irq2 interrupt requests disabled 0 = irq2 interrupt requests enabled mode2 ? irq2 edge/level select bit this read/write bit cont rols the triggering se nsitivity of the irq2 pin. reset clears mode2. 1 = irq2 interrupt requests on falling edges and low levels 0 = irq2 interrupt requests on falling edges only
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor keyboard interrupt module (kbi) 343 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 20. keyboard interrupt module (kbi) 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 20.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 20.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 20.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345 20.5.1 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 20.6 keyboard interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . 347 20.6.1 keyboard status and control register. . . . . . . . . . . . . . . . 348 20.6.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 349 20.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 20.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349 20.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349 20.10 keyboard module during break inte rrupts . . . . . . . . . . . . . . . 350 20.2 introduction the keyboard interrupt module (kbi ) provides eight independently maskable external interrupts whic h are accessible via ptd0?ptd7. when a port pin is enabled for keyboard interr upt function, an internal 30k ? pullup device is also enabled on the pin.
keyboard interrupt module (kbi) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 344 keyboard interrupt module (kbi) freescale semiconductor 20.3 features features of the keyboard interr upt module inclu de the following: eight keyboard interrupt pins with pullup devices separate keyboard in terrupt enable bits and one keyboard interrupt mask programmable edge-only or edge- and level- interrupt sensitivity exit from low-lower modes 20.4 i/o pins the eight keyboard interrupt pins are shar ed with standard port i/o pins. the full name of the kbi pins are listed in table 20-1 . the generic pin name appear in the te xt that follows. addr.register name bit 7654321bit 0 $001a keyboard status and control register (kbscr) read:0000 keyf 0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 20-1. kbi i/o register summary table 20-1. pin name conventions kbi generic pin name full mcu pin name pin selected for kbi function by kbiex bit in kbier kbi0?kbi7 ptd0/kbi0?ptd7/kbi7 kbie0?kbie7
keyboard interrupt module (kbi) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor keyboard interrupt module (kbi) 345 20.5 functional description figure 20-2. keyboard in terrupt block diagram writing to the kbie7?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port d pin as a keyboard interrupt pin. enabling a keyboard interrupt pin in port d also enables its internal pull-up device. a logi c 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched w hen one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is e dge-sensitive only, a falling edge on a keyboard pin does not latch an in terrupt reques t if another keyboard pin is already low. to pr event losing an interrupt request on one pin because another pin is still low, software can disable the latter pin wh ile it is low. if the keyboard interrupt is falli ng edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modek bit is set, the keyboard interrupt pins ar e both falling edge- and low level-sensitive, and both of t he following actions must occur to clear a keyboard interrupt request: kbie0 kbie7 . . . dq ck clr v dd modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kbi7 kbi0 synchronizer keyf keyboard interrupt request to pullup enable to pullup enable
keyboard interrupt module (kbi) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 346 keyboard interrupt module (kbi) freescale semiconductor vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowle dge signal by writing a logic 1 to t he ackk bit in the keyboa rd status and control register kbscr. the ackk bit is useful in app lications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine can al so prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackk bi t latches another inte rrupt request. if the keyboard interrupt mask bit, imask k, is clear, the cpu loads the program counter with the vector address at locations $ffe0 and $ffe1. return of all enabled keyboard interr upt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the key board interrupt pin is falling-edge- sensitive only. with mo dek clear, a vector fetc h or software clear immediately clears the ke yboard interrupt request. reset clears the keyboard interrupt request and the modek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the ke yboard status and control register can be used to see if a pending inte rrupt exists. the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications wh ere polling is preferred. to determine the logi c level on a keyboard inte rrupt pin, use the data direction register to configure the pin as an input and read the data register. note: setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an inpu t, overriding t he data direction register. however, the dat a direction register bi t must be a logic 0 for software to read the pin.
keyboard interrupt module (kbi) keyboard interrupt registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor keyboard interrupt module (kbi) 347 20.5.1 keyboard initialization when a keyboard interrupt pin is enabl ed, it takes time for the internal pull-up to reach a logic 1. therefor e a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by se tting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edg e-triggered pin can be acknowledged immediately after enabling the pin. an interrupt si gnal on an edge- and level-triggered interrupt pin must be acknowledged afte r a delay that depends on the external load. another way to avoi d a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddr bits in data di rection register. 2. write logic 1s to the appropr iate data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 20.6 keyboard in terrupt registers two registers control the operation of the ke yboard interrupt module: keyboard status and c ontrol register ? $001a keyboard interrupt en able register ? $001b
keyboard interrupt module (kbi) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 348 keyboard interrupt module (kbi) freescale semiconductor 20.6.1 keyboard stat us and control register flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity keyf ? keyboard flag bit this read-only bit is set when a keyboard interrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a logic 1 to th is write-only bit clears the keyboard interrupt request. ackk always reads as logic 0. rese t clears ackk. imaskk ? keyboard interrupt mask bit writing a logic 1 to th is read/write bit prev ents the output of the keyboard interrupt mask from gene rating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard tri ggering sensitivity bit this read/write bit controls the tri ggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt reques ts on falling edges and low levels 0 = keyboard interrupt requests on falling edges only address: $001a bit 7654321bit 0 read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 = unimplemented figure 20-3. keyboard status and control regi ster (kbscr)
keyboard interrupt module (kbi) low-power modes mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor keyboard interrupt module (kbi) 349 20.6.2 keyboard inte rrupt enable register the port-d keyboard interrup t enable register enables or disables each port-d pin to operate as a keyboard interrupt pin. kbie7?kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corres ponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = kbix pin enabled as keyboard interrupt pin 0 = kbix pin not enabled as keyboar d interrupt pin 20.7 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. 20.7.1 wait mode the keyboard interrupt module remains ac tive in wait m ode. clearing the imaskk bit in the keyboar d status and control r egister enables keyboard interrupt requests to brin g the mcu out of wait mode. 20.7.2 stop mode the keyboard interrupt module remain s active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to br ing the mcu out of stop mode. address: $001b bit 7654321bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 20-4. keyboard interr upt enable register (kbier)
keyboard interrupt module (kbi) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 350 keyboard interrupt module (kbi) freescale semiconductor 20.8 keyboard module during break interrupts the system integration module (sim) controls whether the keyboard interrupt latch can be cleared during t he break state. the bcfe bit in the sim break flag control regi ster (bfcr) enables soft ware to clear status bits during the break state. to allow software to clear the key board interrupt la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared w hen the mcu exits the break state. to protect the latch during the break st ate, write a logi c 0 to the bcfe bit. with bcfe at logi c 0 (its default state), writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break state has no effect.
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor computer operating properly (cop) 351 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 21. computer operating properly (cop) 21.1 contents 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 21.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352 21.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 21.4.1 iclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 21.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 21.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 21.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 21.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 21.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 21.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 21.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 354 21.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 21.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 21.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 21.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 21.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356 21.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356 21.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 356 21.2 introduction the computer operating properly (cop ) module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runa way code. prevent a cop reset by clearing the cop counter periodically. the cop module can be disabled through the copd bit in the configuration register 1 (config1).
computer operating properly (cop) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 352 computer operating properly (cop) freescale semiconductor 21.3 functional description figure 21-1 shows the structure of the cop module. figure 21-1. cop block diagram the cop counter is a free-running 6- bit counter preceded by a 12-bit prescaler counter. if not cleared by software, the cop counter overflows and generates an asynchr onous reset after 2 18 ?2 4 or 2 13 ?2 4 iclk cycles, depending on the state of the cop rate select bit, coprs, in the config1 register. with a 2 13 ?2 4 iclk cycle overflow option, a 24-khz iclk gives a cop timeout period of 341ms. writing any value to location $ffff before an overflow occurs pr events a cop reset by clearing the cop counter and stages 12 through 5 of the prescaler. note: service the cop immediately after re set and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. copctl write iclk reset vector fetch reset circuit reset status register internal reset sources 12-bit cop prescaler clear all stages 6-bit cop counter cop disable reset copctl write clear copen (from sim) cop counter cop clock cop timeout stop instruction (copd from config1) cop rate sel (coprs from config1) clear stages 5?12
computer operating properly (cop) i/o signals mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor computer operating properly (cop) 353 a cop reset pulls the rst pin low for 32 iclk cycl es and sets the cop bit in the sim reset st atus register (srsr). in monitor mode, the cop is disabled if the rst pin or the irq1 is held at v tst . during the br eak state, v tst on the rst pin disables the cop. note: place cop clearing instructions in the main program and not in an interrupt subroutine. su ch an interrupt subrout ine could keep the cop from generating a reset even while the main pr ogram is not working properly. 21.4 i/o signals the following paragraphs descri be the signals shown in figure 21-1 . 21.4.1 iclk iclk is the internal oscillator output signal. ic lk frequency is approximately equal to 24khz. see section 24. electrical specifications for iclk parameters. 21.4.2 stop instruction the stop instruction cl ears the cop prescaler. 21.4.3 copctl write writing any value to the cop c ontrol register (copctl) (see 21.5 cop control register ) clears the cop counter a nd clears bits 12 through 5 of the prescaler. reading the cop cont rol register retu rns the low byte of the reset vector. 21.4.4 power-on reset the power-on reset (por) circuit clea rs the cop prescaler 4096 iclk cycles after power-up.
computer operating properly (cop) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 354 computer operating properly (cop) freescale semiconductor 21.4.5 internal reset an internal reset clears the co p prescaler and the cop counter. 21.4.6 reset vector fetch a reset vector fetch occurs when the vector addres s appears on the data bus. a reset vector fetch clears the cop prescaler. 21.4.7 copd (cop disable) the copd signal reflec ts the state of the cop di sable bit (copd) in the config1 register. (see figure 21-2 and section 5. configuration and mask option registers (config & mor) .) 21.4.8 coprs (cop rate select) the coprs signal reflects the state of the cop ra te select bit (coprs) in the config1 register. coprs ? cop rate select coprs selects the cop time-out period. reset clears coprs. 1 = cop time out period = 2 13 ? 2 4 iclk cycles 0 = cop time out period = 2 18 ? 2 4 iclk cycles copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: coprs lvistop lvirstd lvipwrd lvi5or3 ssrec stop copd write: reset:00000*000 * reset by por only. figure 21-2. configurati on register 1 (config1)
computer operating properly (cop) cop control register mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor computer operating properly (cop) 355 21.5 cop control register the cop control register is locat ed at address $ffff and overlaps the reset vector. writing any value to $ffff clears t he cop counter and starts a new timeout per iod. reading location $ffff returns the low byte of the reset vector. 21.6 interrupts the cop does not generate cpu interrupt requests. 21.7 monitor mode when monitor mode is entered with v tst on the irq1 pin, the cop is disabled as long as v tst remains on the irq1 pin or the rst pin. when monitor mode is enter ed by having blank rese t vectors and not having v tst on the irq1 pin, the cop is automati cally disabled until a por occurs. 21.8 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 21-3. cop cont rol register (copctl)
computer operating properly (cop) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 356 computer operating properly (cop) freescale semiconductor 21.8.1 wait mode the cop remains active during wait mode. to prevent a cop reset during wait mode, periodi cally clear the cop counter in a cpu interrupt routine. 21.8.2 stop mode stop mode turns off t he iclk input to the cop and clears the cop prescaler. service the co p immediately before ent ering or after exiting stop mode to ensure a full cop timeout period a fter entering or exiting stop mode. to prevent inadvertently turning off t he cop with a stop instruction, a configuration option is av ailable that disables the stop instruction. when the stop bit in the config uration register has the stop instruction is disabled, execution of a stop in struction results in an illegal opcode reset. 21.9 cop module during break mode the cop is disabled during a break interrupt when v tst is present on the rst pin.
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor low-voltage inhibit (lvi) 357 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 22. low-voltage inhibit (lvi) 22.1 contents 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 22.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 22.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 22.4.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 22.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . .360 22.4.3 voltage hysteresis protection . . . . . . . . . . . . . . . . . . . . . . 360 22.4.4 lvi trip selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 22.5 lvi status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 22.6 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361 22.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 22.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 22.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 22.2 introduction this section describes the low-vo ltage inhibit (lvi) module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls below the lv i trip falli ng voltage, v tripf . 22.3 features features of the lvi module include: programmable lvi reset selectable lvi trip voltage programmable st op mode operation
low-voltage inhibit (lvi) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 358 low-voltage inhibit (lvi) freescale semiconductor 22.4 functional description figure 22-2 shows the structur e of the lvi module. the lvi is enabled out of reset. the lvi module cont ains a bandgap reference circuit and comparator. clearing t he lvi power disable bi t, lvipwrd, enables the lvi to monitor v dd voltage. clearing the lvi re set disable bit, lvirstd, enables the lvi module to generate a reset when v dd falls below a voltage, v tripf . setting the lvi enable in stop mode bit, lvistop, enables the lvi to operate in stop mode. setting th e lvi 5v or 3v trip point bit, lvi5or3, enables the trip point voltage, v tripf , to be configured for 5v operation. cleari ng the lvi5or3 bit enables the trip point voltage, v tripf , to be configured for 3v operation. the actual trip points are shown in section 24. electri cal specifications . figure 22-2. lvi module block diagram addr.register name bit 7654321bit 0 $fe0f low-voltage inhibit status register (lvisr) read: lviout 0000000 write: reset:00000000 = unimplemented figure 22-1. lvi i /o register summary low v dd detector lv i p w r d stop instruction lvi reset v dd > v tripr = 0 v dd v tripf = 1 from config from config1 v dd from config1 lv i 5 o r 3 from config1 to lvisr lv i o u t lv i s to p lv i r s t d
low-voltage inhibit (lvi) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor low-voltage inhibit (lvi) 359 note: after a power-on reset (por) the lvi? s default mode of operation is 3v. if a 5v system is used, the user must set the lv i5or3 bit to raise the trip point to 5v operati on. note that this must be done after every power- on reset since the defaul t will revert back to 3v mode after each power- on reset. if the v dd supply is below the 5v mode trip voltage but above the 3v mode trip voltage when por is released, the mcu will operate because v tripf defaults to 3v m ode after a por. so , in a 5v system care must be taken to ensure that v dd is above the 5v mode trip voltage after por is released. note: if the user requires 5v mode and sets the lvi5or3 bit after a power-on reset while the v dd supply is not above the v tripf for 5v mode, the mcu will immediately go into reset. the lvi in this case will hold the mcu in reset until either v dd goes above the risi ng 5v trip point, v tripr , which will release reset or v dd decreases to approxim ately 0v which will re-trigger the power-on re set and reset the trip point to 3v operation. lvistop, lvipwrd, lv i5or3, and lvirstd are in the configuration register 1 (config1). see section 5. configur ation and mask option registers (config & mor) for details of the lv i?s configuration bits. once an lvi reset occurs, the mcu remains in reset until v dd rises above a voltage, v tripr , which causes the mcu to exit reset. see 9.4.2.5 low-voltage inhibit (lvi) reset for details of the interaction between the sim and the lvi. the output of the comparator controls the state of the lviout flag in t he lvi status register (lvisr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. 22.4.1 polled lvi operation in applications that can operate at v dd levels below the v tripf level, software can monitor v dd by polling the lviout bi t. in the configuration register 1 (config1), t he lvipwrd bit must be at logic 0 to enable the lvi module, and the lvi rstd bit must be at lo gic 1 to disable lvi resets.
low-voltage inhibit (lvi) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 360 low-voltage inhibit (lvi) freescale semiconductor 22.4.2 forced reset operation in applications that require v dd to remain above the v tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls below the v tripf level. in the configurat ion register 1 (config1), the lvipwrd and lvirstd bits must be at logi c 0 to enable the lvi module and to enable lvi resets. 22.4.3 voltage hyst eresis protection once the lvi has triggered (by having v dd fall below v tripf ), the lvi will maintain a reset condition until v dd rises above the rising trip point voltage, v tripr . this prevents a condition in which the mcu is continually entering and exiting reset if v dd is approximately equal to v tripf . v tripr is greater than v tripf by the hysteresis voltage, v hys . 22.4.4 lvi trip selection the lvi5or3 bit in the config1 regi ster selects whether the lvi is configured for 5v or 3v protection. note: the mcu is guaranteed to oper ate at a minimum suppl y voltage. the trip point (v tripf [5 v] or v tripf [3 v]) may be lower than this. (see section 24. electri cal specifications for the actual trip point voltages.)
low-voltage inhibit (lvi) lvi status register mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor low-voltage inhibit (lvi) 361 22.5 lvi status register the lvi status register (l visr) indicates if the v dd voltage was detected below the v tripf level. lviout ? lvi output bit this read-only flag be comes set when the v dd voltage falls below the v tripf trip voltage (see table 22-1). reset clears the lviout bit. 22.6 lvi interrupts the lvi module does not gener ate interrupt requests. 22.7 low-power modes the stop and wait instructions put the mcu in low power- consumption standby modes. address: $fe0f bit 7654321bit 0 read: lviout 0 0 0 0 0 0 0 write: reset:00000000 = unimplemented figure 22-3. lvi status register table 22-1. lviout bit indication v dd lviout v dd > v tripr 0 v dd < v tripf 1 v tripf < v dd < v tripr previous value
low-voltage inhibit (lvi) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 362 low-voltage inhibit (lvi) freescale semiconductor 22.7.1 wait mode if enabled, the lvi module remains acti ve in wait mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. 22.7.2 stop mode if enabled in stop mode (l vistop = 1), the lvi module remains active in stop mode. if enabled to generat e resets (lvirstd = 0), the lvi module can generate a reset and bri ng the mcu out of stop mode.
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor break module (brk) 363 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 23. break module (brk) 23.1 contents 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 23.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 23.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364 23.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 366 23.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .366 23.4.3 tim1 and tim2 during break interr upts. . . . . . . . . . . . . . . 366 23.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 366 23.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 23.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366 23.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367 23.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 23.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 367 23.6.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 368 23.6.3 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 368 23.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . 370 23.2 introduction this section describes the break module. the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
break module (brk) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 364 break module (brk) freescale semiconductor 23.3 features features of the br eak module include: accessible input/output (i/o) regi sters during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 23.4 functional description when the internal address bus matches the value written in the break address registers, the br eak module issues a breakpoint signal to the cpu. the cpu then loads the instruct ion register with a software interrupt instruction (swi) afte r completion of the current cpu instruction. the progr am counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu-generated address (the addr ess in the program counter) matches the contents of th e break address registers. software writes a logic 1 to the brka bit in the break status and control register. when a cpu-generated addre ss matches the contents of the break address registers, th e break interrupt begins af ter the cpu completes its current instruction. a return-from-inter rupt instruction (r ti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 23-1 shows the structure of the break module.
break module (brk) functional description mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor break module (brk) 365 figure 23-1. break module block diagram iab15?iab8 iab7?iab0 8-bit comparator 8-bit comparator control break address register low break address register high iab15?iab0 break addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe0c break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved figure 23-2. break module i/o register summary
break module (brk) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 366 break module (brk) freescale semiconductor 23.4.1 flag protectio n during break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. 23.4.2 cpu during break interrupts the cpu starts a br eak interrupt by: loading the instruction regist er with the swi instruction loading the program count er with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 23.4.3 tim1 and tim2 du ring break interrupts a break interrupt stops the timer counters. 23.4.4 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 23.5 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. 23.5.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the re turn address on the stack if sbsw is set (see section 9. system in tegration module (sim) ). clear the sbsw bit by writi ng logic 0 to it.
break module (brk) break module registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor break module (brk) 367 23.5.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. 23.6 break module registers these registers control and monitor operation of the break module: break status and cont rol register (brkscr) break address regi ster high (brkh) break address regi ster low (brkl) sim break status register (sbsr) sim break flag con trol register (sbfcr) 23.6.1 break status and control register the break status and control register (brkscr) contai ns break module enable and status bits. brke ? break enable bit this read/write bit enabl es breaks on break address register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16 -bit address match 0 = breaks disabled on 16-bit address match address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 23-3. break status an d control register (brkscr)
break module (brk) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 368 break module (brk) freescale semiconductor brka ? break active bit this read/write status and control bit is se t when a break address match occurs. writing a logic 1 to brka generates a br eak interrupt. clear brka by writing a l ogic 0 to it before exit ing the break routine. reset clears the brka bit. 1 = (when read) br eak address match 0 = (when read) no break address match 23.6.2 break addr ess registers the break address register s (brkh and brkl) contai n the high and low bytes of the desired brea kpoint address. reset clears the break address registers. 23.6.3 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from wait mode. the flag is useful in applications requiring a return to wait mode a fter exiting from a break interrupt. address: $fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 23-4. break addres s register high (brkh) address: $fe0d bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 23-5. break addr ess register low (brkl)
break module (brk) break module registers mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor break module (brk) 369 sbsw ? break wait bit this status bit is set w hen a break interrupt c auses an exit from wait mode or stop mode. clear sb sw by writing a logic 0 to it. reset clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break interrupt routine. the user can modify the return address on the st ack by subtractin g 1 from it. the following code is an example. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. r= reserved figure 23-6. sim break stat us register (sbsr) ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register.
break module (brk) data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 370 break module (brk) freescale semiconductor 23.6.4 sim break flag control register the sim break flag control register (s bfcr) contains a bit that enables software to clear status bits wh ile the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear st atus bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 23-7. sim break flag c ontrol register (sbfcr)
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor electrical specifications 371 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 24. electrical specifications 24.1 contents 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 24.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 372 24.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 373 24.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 24.6 5.0v dc electrical charac teristics . . . . . . . . . . . . . . . . . . . . . 374 24.7 3.0v dc electrical charac teristics . . . . . . . . . . . . . . . . . . . . . 376 24.8 5.0v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 24.9 3.0v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 24.10 5.0v oscillator characte ristics . . . . . . . . . . . . . . . . . . . . . . . . 378 24.11 3.0v oscillator characte ristics . . . . . . . . . . . . . . . . . . . . . . . . 379 24.12 5.0v adc electrical c haracteristics . . . . . . . . . . . . . . . . . . . .380 24.13 3.0v adc electrical c haracteristics . . . . . . . . . . . . . . . . . . . .381 24.14 analog module electrical characterist ics . . . . . . . . . . . . . . . . 382 24.14.1 temperature sensor electrical characteristic s . . . . . . . . . 382 24.14.2 current detection el ectrical characteristics. . . . . . . . . . . . 382 24.14.3 two-stage amplifier el ectrical characteristic s. . . . . . . . . . 382 24.15 timer interface module characteristics . . . . . . . . . . . . . . . . . 383 24.16 mmiic electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . 383 24.17 cgm electrical s pecifications. . . . . . . . . . . . . . . . . . . . . . . . . 385 24.18 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 386
electrical specifications data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 372 electrical specifications freescale semiconductor 24.2 introduction this section contains electrical and timing specifications. 24.3 absolute maximum ratings maximum ratings are t he extreme limits to which the mcu can be exposed without perman ently damaging it. note: this device is not guar anteed to operate properly at the maximum ratings. refer to 24.6 5.0v dc electri cal characteristics for guaranteed operating conditions. note: this device contains circ uitry to protect the i nputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applic ation of any voltage higher than maximum-rated voltages to this hi gh-impedance circui t. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are co nnected to an appropriate logic voltage level (for example, either v ss or v dd .) table 24-1. absolute maximum ratings (1) notes : 1. voltages referenced to v ss . characteristic symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage all pins (except irq1 ) irq1 pin v in v ss ?0.3 to v dd +0.3 v ss ?0.3 to 8.5 v maximum current per pin excluding v dd and v ss i 25 ma maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma storage temperature t stg ?55 to +150 c
electrical specifications functional operating range mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor electrical specifications 373 24.4 functional operating range 24.5 thermal characteristics table 24-2. operating range characteristic symbol value unit operating temperature range t a ? 40 to +125 ? 40 to +85 c operating voltage range v dd ? 5v 10% 3v 10% (1) 5v 10% notes : 1. a minimum operating v dd of 3v is required to achieve the adc module specifications stated in table 24-11 . 3v adc elect rical characteristics . v table 24-3. thermal characteristics characteristic symbol value unit thermal resistance 42-pin sdip 48-pin lqfp ja 60 80 c/w c/w i/o pin power dissipation p i/o user determined w power dissipation (1) notes : 1. power dissipation is a function of temperature. p d p d = (i dd v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k constant unique to the device. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c) + p d 2 ja w/ c average junction temperature t j t a + (p d ja ) c
electrical specifications data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 374 electrical specifications freescale semiconductor 24.6 5.0v dc electrical characteristics table 24-4. 5v dc el ectrical characteristics characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?2.0 ma) pta[0:7], ptb[4:6], ptc[0:7], ptd[0:7] v oh v dd ?0.8 ??v output low voltage (i load = 1.6ma) pta[0:7], ptb[0:6], ptc[0:7], ptd[0:7] v ol ??0.4v led sink current (v drain = 4.0v) pta[0:5], ptc[3:7] i ol ??15?ma input high voltage pta[0:7], ptb[0:6], pt c[0:7], ptd[0:7], rst , irq1 , irq2 , osc1. v ih 0.7 v dd ? v dd v input low voltage pta[0:7], ptb[0:6], pt c[0:7], ptd[0:7], rst , irq1 , irq2 , osc1 v il v ss ? 0.3 v dd v v dd supply current run (3) , f op = 8.0 mhz with adc on with adc off wait (4) , f op = 8.0 mhz stop (5) 25 c (with osc, tbm, current sense, lvi) 25 c (with osc, tbm, current sense) 25 c (with osc, tbm) 25 c ?40 c to 85 c (with osc, tbm, current sense, lvi) ?40 c to 85 c (with osc, tbm, current sense) ?40 c to 85 c (with osc, tbm) ?40 c to 85 c ?40 c to 125 c (with osc, tbm, current sense, lvi) ?40 c to 125 c (with osc, tbm, current sense) ?40 c to 125 c (with osc, tbm) ?40 c to 125 c i dd ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 24 18 7.5 50 12 9 1 ? ? ? ? ? ? ? ? 40 30 15 150 40 30 10 180 50 40 15 200 60 50 25 ma ma ma a a a a a a a a a a a a digital i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por re-arm voltage (6) v por 0?100mv
electrical specifications 5.0v dc electrical characteristics mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor electrical specifications 375 por rise-time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v tst 1.4 v dd ?8v pullup resistors (8) ptd[0:7] configured as kbi[0:7] rst , irq1 , irq2 r pu1 r pu2 24 24 35 35 42 42 k ? k ? low-voltage inhibit, trip falling voltage v lvii5 3.80 4.15 4.45 v low-voltage inhibit, trip rising voltage v lvii5 3.95 4.30 4.60 v schmitt trigger input low level trip voltage rst , irq1 , irq2 , kbi[0:7] v scmtl ?1.21? v schmitt trigger input high level trip voltage rst , irq1 , irq2 , kbi[0:7] v scmth ?1.65? v notes : 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as in puts. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source. all inpu ts 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as in puts. osc2 capacitance linearly affects wait i dd . 5. stop i dd measured with osc1 grounded, no port pins sourcing current. 6. maximum is highest vo ltage that por is guaranteed. 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. 8. r pu1 and r pu2 are measured at v dd = 5.0v table 24-4. 5v dc el ectrical characteristics characteristic (1) symbol min typ (2) max unit
electrical specifications data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 376 electrical specifications freescale semiconductor 24.7 3.0v dc electrical characteristics table 24-5. 3v dc el ectrical characteristics characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?1.0ma) pta[0:7], ptb[4:6], ptc[0:7], ptd[0:7] v oh v dd ?0.4 ??v output low voltage (i load = 0.8ma) pta[0:7], ptb[0:6], ptc[0:7], ptd[0:7] v ol ??0.4v led sink current (v drain = 2.0v) pta[0:5], ptc[3:7] v ol ??5?ma input high voltage pta[0:7], ptb[0:6], pt c[0:7], ptd[0:7], rst , irq1 , irq2 , osc1 v ih 0.7 v dd ? v dd v input low voltage pta[0:7], ptb[0:6], pt c[0:7], ptd[0:7], rst , irq1 , irq2 , osc1 v il v ss ? 0.3 v dd v v dd supply current run (3) , f op = 4.0 mhz with adc on with adc off wait (4) , f op = 4.0 mhz stop (5) 25 c (with osc, tbm, lvi) 25 c (with osc, tbm) 25 c ?40 c to 85 c (with osc, tbm, lvi) ?40 c to 85 c (with osc, tbm) ?40 c to 85 c i dd ? ? ? ? ? ? ? ? ? 7 5 2.5 27 5 0.5 ? ? ? 16 12 6 80 12 5 100 15 5 ma ma ma a a a a a a digital i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por re-arm voltage (6) v por 0?100mv por rise-time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v hi 1.4 v dd ? 2.0 v dd v pullup resistors (8) ptd[0:7] configured as kbi[0:7] rst , irq1 , irq2 r pu1 r pu2 24 24 35 35 42 42 k ? k ?
electrical specifications 5.0v control timing mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor electrical specifications 377 24.8 5.0v control timing 24.9 3.0v control timing low-voltage inhibit, trip voltage (no hysteresis implemented for 3v lvi) v lv i 3 2.32 2.49 2.68 v schmitt trigger input low level trip voltage rst , irq1 , irq2 , kbi[0:7] v scmtl ?0.8?v schmitt trigger input high level trip voltage rst , irq1 , irq2 , kbi[0:7] v scmth ?1.2?v notes : 1. v dd = 2.7 to 3.3 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as in puts. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source. all inpu ts 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as in puts. osc2 capacitance linearly affects wait i dd . 5. stop i dd measured with osc1 grounded, no port pins sourcing current. 6. maximum is highest vo ltage that por is guaranteed. 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. 8. r pu1 and r pu2 are measured at v dd = 5.0v. table 24-6. 5v control timing characteristic (1) notes : 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit internal operating frequency (2) 2. some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. f op ?8.0mhz rst input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 750 ? ns table 24-7. 3v control timing characteristic (1) notes : 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit internal operating frequency (2) 2. some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. f op ?4.0mhz rst input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 1.5 ? s table 24-5. 3v dc el ectrical characteristics characteristic (1) symbol min typ (2) max unit
electrical specifications data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 378 electrical specifications freescale semiconductor 24.10 5.0v oscillator characteristics figure 24-1. rc vs. bus frequency (5v @25 c) table 24-8. 5v oscillator specifications characteristic symbol min typ max unit internal oscillator clock frequency f iclk 19.2k 24k 28.8k hz external reference clock to osc1 (1) notes : 1. no more than 10% duty cycle deviation from 50%. f osc dc ? 20m hz crystal reference frequency (2) 2. fundamental mode crystals only. f xclk 32.768k 4.9152m hz crystal load capacitance (3) 3. consult crystal manufacturer?s data. c l ??? crystal fixed capacitance c 1 ? 2 c l (25p) ?f crystal tuning capacitance c 2 ? 2 c l (25p) ?f feedback bias resistor r b ?10m? ? series resistor (4) 4. not required for high frequency crystals. r s ?100k? ? external rc clock frequency f rcclk 2m ? 18m hz external resistor r ext see figure 24-1 ? external capacitor c ext ?10?pf r ext c ext osc1 v dd mcu 0 0246810 5 4 3 2 1 resistor r ext (k ? ) bus frequency, f op (mhz) c ext = 10 pf 5v @ 25 c f rcclk = f op 4
electrical specifications 3.0v oscillator characteristics mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor electrical specifications 379 24.11 3.0v oscillator characteristics figure 24-2. rc vs. bus frequency (3v @25 c) table 24-9. 3v oscillator specifications characteristic symbol min typ max unit internal oscillator clock frequency f iclk 13.8k 17.2k 20.6k hz external reference clock to osc1 (1) notes : 1. no more than 10% duty cycle deviation from 50%. f osc dc ? 16m hz crystal reference frequency (2) 2. fundamental mode crystals only. f xclk 32.768k 4.9152m hz crystal load capacitance (3) 3. consult crystal manufacturer?s data. c l ??? crystal fixed capacitance c 1 ? 2 c l (25p) ?f crystal tuning capacitance c 2 ? 2 c l (25p) ?f feedback bias resistor r b ?10m? ? series resistor (4) 4. not required for high frequency crystals. r s ?100k? ? external rc clock frequency f rcclk 2m ? 10m hz external resistor r ext see figure 24-2 ? external capacitor c ext ?10?pf r ext c ext osc1 v dd mcu 0 0 5 10 15 20 2.5 2 1.5 1 0.5 resistor r ext (k ? ) bus frequency, f op (mhz) f rcclk = f op 4 3 c ext = 10 pf 3v @ 25 c
electrical specifications data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 380 electrical specifications freescale semiconductor 24.12 5.0v adc electrical characteristics table 24-10. 5v adc el ectrical characteristics characteristic symbol min max unit notes supply voltage v dda 4.5 5.5 v v dda is an dedicated pin and should be tied to v dd on the pcb with proper decoupling. input range v adin 0 v dda v v adin v dda resolution b ad 10 10 bits absolute accuracy a ad ? 1.5 lsb includes quantization. 0.5 lsb = 1 adc step. adc internal clock f adic 500k 2m hz t adic = 1/f adic conversion range r ad v refl v refh v adc voltage reference high v refh ? v dda + 0.1 v adc voltage reference low v refl v ssa ? 0.1 ?v conversion time t adc 16 17 t adic cycles sample time t ads 5? t adic cycles monotonicity m ad guaranteed zero input reading z adi 000 001 hex v adin = v refl full-scale reading f adi 3fd 3ff hex v adin = v refh input capacitance c adi ? 20 pf not tested. input impedance r adi 20m ? ? v refh /v refl i vref ? 1.6 ma not tested.
electrical specifications 3.0v adc electrical characteristics mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor electrical specifications 381 24.13 3.0v adc electrical characteristics table 24-11. 3v adc el ectrical characteristics characteristic symbol min max unit notes supply voltage v dda 3.0 3.3 v v dda is an dedicated pin and should be tied to v dd on the pcb with proper decoupling. input range v adin 0 v dda v v adin v dda resolution b ad 10 10 bits absolute accuracy a ad ? 1.5 lsb includes quantization. 0.5 lsb = 1 adc step. adc internal clock f adic 500 k 2 m hz t adic = 1/f adic conversion range r ad v refl v refh v adc voltage reference high v refh ? v dda + 0.1 v adc voltage reference low v refl v ssa ? 0.1 ?v conversion time t adc 16 17 t adic cycles sample time t ads 5? t adic cycles monotonicity m ad guaranteed zero input reading z adi 000 001 hex v adin = v refl full-scale reading f adi 3fd 3ff hex v adin = v refh input capacitance c adi ? 20 pf not tested. input impedance r adi 20m ? ? measured at 5v v refh /v refl i vref ? 1.6 ma not tested.
electrical specifications data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 382 electrical specifications freescale semiconductor 24.14 analog module el ectrical characteristics 24.14.1 temperature sensor el ectrical characteristics 24.14.2 current detection el ectrical characteristics 24.14.3 two-stage amplifier electrical characteristics table 24-12. temperature sensor electrical c haracteristics characteristic symbol min typ max unit temperature range ?20 ? 70 c temperature slope v dd =5v 10%, gaina=2, gainb=6 v dd =3v 10%, gaina=2, gainb=4 1.275 1.048 1.338 1.089 1.372 1.146 adc steps/ c table 24-13. current detecti on electrical characteristics characteristic symbol min typ max unit trip point (1) notes : 1. the current detect comparator is designed for v dd =5v 10% only. v det ?6 ? +12 mv table 24-14. two-stage amplifi er electrical characteristics characteristic symbol min typ max unit amplifier input signal hold time t amh 10 + [(gaina ? 1) 2] t am cycles (1) notes : 1. t am is the amclk. amplifier response time t amr 70 + (8 gaina) + (6 gainb) t am cycles amplifier gain tolerance v dd =5v 10%, gaina=4, gainb=16 v in = 10mv to 30mv v in = 30mv to 65mv v dd =5v 10%, gaina=6, gainb=16 v in = 10mv to 30mv v in = 30mv to 44mv v dd =3v 10%, gaina=4, gainb=16 v in = 10mv to 38mv v dd =3v 10%, gaina=6, gainb=16 v in = 10mv to 24mv ?3.5 ?1.5 ?3.5 ?1.5 ?3.5 ?3.5 ? ? ? ? ? ? +3.5 +1.5 +3.5 +1.5 +3.5 +3.5 %
electrical specifications timer interface module characteristics mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor electrical specifications 383 24.15 timer interface module characteristics 24.16 mmiic electrical characteristics figure 24-3. mmii c signal timings see table 24-16 for mmiic timing parameters. characteristic symbol min max unit input capture pulse width t tih , t til 1? t cyc table 24-15. mmiic dc el ectrical characteristics characteristic (1) notes : 1. v dd = 2.7 to 5.5vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol min typ max unit comments input low v il ?0.5 0.8 v data, clock input low. input high v ih 2.1 5.5 v data, clock input high. output low v ol 0.4 v data, clock output low; @i pullup,max input leakage i leak 5 a input leakage current pullup current i pullup 100 350 a current through pull-up resistor or current source. see note. (2) 2. the i pullup (max) specification is determined primarily by the need to accommodate a maximum of 1.1k ? equivalent se- ries resistor of removable smbu s devices, such as the smart ba ttery, while maintaining the v ol (max) of the bus. t hd.sta t low t high t su.dat t hd.dat t su.sto sda scl t su.sta
electrical specifications data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 384 electrical specifications freescale semiconductor table 24-16. mmiic interface i nput/output si gnal timing characteristic symbol min typ max unit comments operating frequency f smb 10 100 khz mmiic operating frequency bus free time t buf 4.7 s bus free time between stop and start condition repeated start hold time. t hd.sta 4.0 s hold time after (repeated) start condition. after this period, the first clock is generated. repeated start setup time. t su.sta 4.7 s repeated start condition setup time. stop setup time t su.sto 4.0 s stop condition setup time. hold time t hd.dat 300 ns data hold time. setup time t su.dat 250 ns data setup time. clock low time-out t timeout 25 35 ms clock low time-out. (1) clock low t low 4.7 s clock low period clock high t high 4.0 s clock high period. (2) slave clock low extend time t low.sext 25 ms cumulative clock low extend time (slave device) (3) master clock low extend time t low.mext 10 ms cumulative clock low extend time (master device) (4) fall time t f 300 ns clock/data fall time (5) rise time t r 1000 ns clock/data rise time (5) notes : 1. devices participating in a transfer will timeout when any clock low exceeds the value of t timeout min. of 25ms. devices that have detected a timeout condition mu st reset the communication no later than t timeout max of 35ms. the maximum value specified must be adhered to by both a master and a sl ave as it incorporates the cumu lative limit for both a master (10 ms) and a slave (25 ms). software should turn-off the mmiic modu le to release the sda and scl lines. 2. t high max provides a simple guaranteed method for devices to detect the idle conditions. 3. t low.sext is the cumulative time a slave device is allowed to ext end the clock cycles in one message from the initial start to the stop. if a slave device exceeds this time, it is expected to release both its clock and data lines and reset itself. 4. t low.mext is the cumulative time a master devi ce is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, a ck-to-ack, or ack-to-stop. 5. rise and fall time is defined as follows: t r = (v ilmax ? 0.15) to (v ihmin + 0.15), t f = 0.9 v dd to (v ilmax ? 0.15).
electrical specifications cgm electrical specifications mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor electrical specifications 385 24.17 cgm electrical specifications characteristic symbol min typ max unit reference frequency f rdv 30 32.768 100 khz range nominal multiplies f nom ? 38.4 ? khz vco center-of-range frequency f vrs 38.4k ? 40.0m hz vco range linear range multiplier l 1 ? 255 vco power-of-two-range multiplier 2 e 1? 4 vco multiply factor n 1 ? 4095 vco prescale multiplier 2 p 1?8 reference divider factor r 1 1 15 vco operating frequency f vclk 38.4k ? 40.0m hz manual acquisition time t lock ??50ms automatic lock time t lock ??50ms automatic lock time wake up from stop with osc enabled (1) notes : 1. test condition: v dd = 5.0vdc / 3.0vdc, v ss = 0 vdc. reference frequency = 32.768khz, locking to 4mhz bus frequency. t lock ?1015ms pll jitter (2) 2. deviation of average bus freq uency over 2ms. n = vco multiplier. f j 0? f rclk 0.025% 2 p n/4 hz
electrical specifications data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 386 electrical specifications freescale semiconductor 24.18 flash memory characteristics table 24-17. flash memory electrical characteristics characteristic symbol min. max. unit data retention voltage v rdr 1.3 ? v number of rows per page 2 rows number of bytes per page 128 bytes read bus clock frequency f read (1) notes : 1. f read is defined as the frequency range for which the flash memory can be read. 32k 8m hz page erase time t erase (2) 2. if the page erase time is longer than t erase (min.), there is no erase-disturb, bu t it reduces the endurance of the flash memory. 1?ms mass erase time t merase (3) 3. if the mass erase time is longer than t merase (min.), there is no erase-disturb, bu t is reduces the endurance of the flash memory. 4?ms pgm/erase to hven setup time t nvs 10 ? s high-voltage hold time t nvh 5? s high-voltage hold time (mass erase) t nvhl 100 ? s program hold time t pgs 5? s program time t prog 30 40 s address/data setup time t ads ?30 ns address/data hold time t adh ?30 ns recovery time t rcv (4) 4. it is defined as the time it needs before the flash can be read after turning off the high vo ltage charge pump, by clearing hven to logic 0. 1? s cumulative hv period t hv (5) 5. t hv is the cumulative high voltage programming time to the sa me row before next erase, and the same address can not be programmed twice before next erase. ? 25ms row erase endurance (6) 6. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase/program cycles. ? 10k ? cycles row program endurance (7) 7. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase/program cycle. ? 10k ? cycles data retention time (8) 8. the flash is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. ?10?years
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor mechanical specifications 387 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 25. mechanical specifications 25.1 contents 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 25.3 48-pin plastic low quad flat pack (lqfp) . . . . . . . . . . . . . . 388 25.4 42-pin shrink dual in -line package (sdip) . . . . . . . . . . . . . . 389 25.2 introduction this section gives t he dimensions for: 48-pin plastic low quad flat pa ck (case #932-02) 42-pin shrink dual in-l ine package (case #858-01)
mechanical specifications data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 388 mechanical specifications freescale semiconductor 25.3 48-pin plastic low quad flat pack (lqfp) figure 25-1. 48-pin lqfp (case #932-02) a a1 z 0.200 ab t?u 4x z 0.200 ac t?u 4x b b1 1 12 13 24 25 36 37 48 s1 s v v1 p ae ae t, u, z detail y detail y base metal n j f d t?u m 0.080 z ac section ae?ae ad g 0.080 ac m top & bottom l w k aa e c h 0.250 r 9 detail ad notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. datum plane ab is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums t, u, and z to be determined at datum plane ab. 5. dimensions s and v to be determined at seating plane ac. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 per side. dimensions a and b do include mold mismatch and are determined at datum plane ab. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.350. 8. minimum solder plate thickness shall be 0.0076. 9. exact shape of each corner is optional. t u z ab ac gauge plane dim a min max 7.000 bsc millimeters a1 3.500 bsc b 7.000 bsc b1 3.500 bsc c 1.400 1.600 d 0.170 0.270 e 1.350 1.450 f 0.170 0.230 g 0.500 bsc h 0.050 0.150 j 0.090 0.200 k 0.500 0.700 m 12 ref n 0.090 0.160 p 0.250 bsc l 1 5 r 0.150 0.250 s 9.000 bsc s1 4.500 bsc v 9.000 bsc v1 4.500 bsc w 0.200 ref aa 1.000 ref
mechanical specifications 42-pin shrink dual in-line package (sdip) mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor mechanical specifications 389 25.4 42-pin shrink dual in-line package (sdip) figure 25-2. 42-pin sdip (case #858-01) ?a? 42 22 121 ?b? seating plane ?t? s a m 0.25 (0.010) t s b m 0.25 (0.010) t l h m j 42 pl d 42 pl f g n k c notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimensions a and b do not include mold flash. maximum mold flash 0.25 (0.010). dim min max min max millimeters inches a 1.435 1.465 36.45 37.21 b 0.540 0.560 13.72 14.22 c 0.155 0.200 3.94 5.08 d 0.014 0.022 0.36 0.56 f 0.032 0.046 0.81 1.17 g 0.070 bsc 1.778 bsc h 0.300 bsc 7.62 bsc j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l 0.600 bsc 15.24 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.02
mechanical specifications data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 390 mechanical specifications freescale semiconductor
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor ordering information 391 data sheet ? mc68hc9 08sr12mc68hc08sr12 section 26. ordering information 26.1 contents 26.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 26.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 26.2 introduction this section contains ordering numbers for the mc68hc908sr12. 26.3 mc order numbers table 26-1. mc order numbers mc order number operating temperature range package mc68hc908sr12cb ?40 c to +85 c 42-pin sdip (1) notes : 1. sdip = shrink dual in-line package. MC68HC908SR12MB (2) 2. temperature grade "m" is available for 5v operating voltage only. ?40 c to +125 c mc68hc908sr12cfa ?40 c to +85 c 48-pin lqfp (3) 3. lqfp = low quad flat pack. mc68hc908sr12mfa (2) ?40 c to +125 c
ordering information data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 392 ordering information freescale semiconductor
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor mc68hc08sr12 393 data sheet ? mc68hc9 08sr12mc68hc08sr12 appendix a. mc68hc08sr12 a.1 contents a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 a.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 a.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 a.5 mask option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 a.6 reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 a.7 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397 a.8 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 a.8.1 5.0v dc electric al characteristics . . . . . . . . . . . . . . . . . . . 398 a.8.2 3.0v dc electric al characteristics . . . . . . . . . . . . . . . . . . . 399 a.8.3 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 a.9 rom order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 394 mc68hc08sr12 freescale semiconductor mc68hc08sr12 a.2 introduction this section introduces the mc68 hc08sr12, the rom part equivalent to the mc68hc908sr12. the entire data book apply to this rom device, with exceptions outlined in this appendix. a.3 mcu block diagram figure a-1 shows the block diagram of the mc68hc08sr12. a.4 memory map the mc68hc08sr12 has 12 ,288 bytes of user rom from $c000 to $efff, and 38 bytes of user rom vectors from $ffda to $ffff. on the mc68hc908sr12, these memory locations are flash memory. figure a-2 shows the memory ma p of the mc68hc08sr12 table a-1. summary of mc68hc08s r12 and mc68hc908sr12 differences mc68hc08sr12 mc68hc908sr12 memory ($c000?$efff) 12,288 bytes rom 12,288 bytes flash user vectors ($ffda?$ffff) 38 bytes rom 38 bytes flash oscillator selection (register at $ff80) mask option register; defined by mask; read only. $ff80 ? mor mask option register; defined by programming flash location $ff80. $ff80 ? mor registers at $fe08 and $ff09 not used; locations are reserved. flash related registers. $fe08 ? flcr $ff09 ? flbpr monitor rom ($fe10?$ff7f) used for testing purposes only. used for testing and flash programming/erasing.
mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor mc68hc08sr12 395 mc68hc08sr12 figure a-1. mc68h c08sr12 block diagram clock generator module system integration module timebase 2-channel timer interface module 2 low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 96 bytes user rom ? 12,288 bytes user ram ? 512 bytes monitor rom ? 368 bytes external irq module ddrb portb internal bus osc1 osc2 cgmxfc * rst * irq1 module interrupt module computer operating properly module v refh ptb6/irq2 ptb5/t2ch1 ptb4/t2ch0 ptb3//scl1/rxd ? ptb2/sda1/txd ? ptb1/scl0 ? ptb0/sda0 ? v refl 2-channel timer interface module 1 phase-locked loop serial communications interface module power-on reset module power v ss v dd v ssa v dda * pin contains integrated pullup device. ** pin contains conf igurable pullup device. *** pin contains integrated pul lup device for kbi functions. ? pin is open-drain when configured as output. ? high current drive pin (for led). # pin not bonded on 42-pin sdip. 10-bit analog-to-digital converter module pulse width modulator module porta ddra pta5/atd7 ? pta0/atd2 ? ddrc portc ptc7/atd12 ? # ptc6/atd11 ? # ptc5/atd10 ? ptc4/atd9 ? ptc3/atd8 ? ptc2/pwm2 ptc1/pwm1 ptc0/pwm0/cd portd ddrd ptd7/kbi7 ? ptd0/kbi0 *** ** irq2 multi-master iic (smbus) interface module analog module opin1/atd0 # opin2/atd1 pta7/t1ch1 pta6/t1ch0 v ssam x-tal oscillator rc oscillator internal oscillator oscillators and user rom vectors ? 38 bytes shaded blocks indicate differences to mc68hc908sr12
data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 396 mc68hc08sr12 freescale semiconductor mc68hc08sr12 $0000 $005f i/o registers 96 bytes $0060 $025f ram 512 bytes $0260 $bfff unimplemented 48,544 bytes $c000 $efff rom 12,288 bytes $f000 $fdff unimplemented 3,584 bytes $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $fe06 interrupt status register 3 (int3) $fe07 reserved $fe08 reserved $fe09 reserved $fe0a reserved $fe0b reserved $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and control register (brkscr) $fe0f lvi status register (lvisr) $fe10 $ff7f monitor rom 368 bytes $ff80 mask option register $ff81 $ffd9 reserved 89 bytes $ffda $ffff rom vectors 38 bytes figure a-2. mc68hc08sr12 memory map
mc68hc08sr12 mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor mc68hc08sr12 397 a.5 mask option register the mask option register (mor) is us ed for selecting on e of the three clock options for the mcu. the mor at $ff80 is a read-only register on the mc68hc08sr12. it is defined by a mask option (hard-wired connection) specified at the same time as t he rom code submission. on the mc68hc908sr12, the mor is a byte loca ted in flash memory, and is written by a flash programming routine. a.6 reserved registers the two registers at $fe 08 and $ff09 are reserv ed locations on the mc68hc08sr12. on the mc68hc908sr12, these two locations are the flash control register and the flash block protect regi ster respectively. a.7 monitor rom the monitor program (monito r rom, $fe10?$ff7f) on the mc68hc08sr12 is for device testing only. a.8 electrical specifications electrical specifications fo r the mc68hc908sr 12 apply to the mc68hc08sr12, except for t he parameters indicated below.
data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 398 mc68hc08sr12 freescale semiconductor mc68hc08sr12 a.8.1 5.0v dc elect rical characteristics table a-2. 5v dc el ectrical characteristics characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?2.0 ma) pta[0:7], ptb[4:6], ptc[0:7], ptd[0:7] v oh v dd ?0.8 ??v output low voltage (i load = 1.6ma) pta[0:7], ptb[0:6], ptc[0:7], ptd[0:7] v ol ??0.4v led sink current (v drain = 4.0v) pta[0:5], ptc[3:7] i ol ??15?ma input high voltage pta[0:7], ptb[0:6], pt c[0:7], ptd[0:7], rst , irq1 , irq2 , osc1. v ih 0.7 v dd ? v dd v input low voltage pta[0:7], ptb[0:6], pt c[0:7], ptd[0:7], rst , irq1 , irq2 , osc1 v il v ss ? 0.3 v dd v v dd supply current run (3) , f op = 8.0 mhz with adc on with adc off wait (4) , f op = 8.0 mhz stop (5) 25 c (with osc, tbm, current sense, lvi) 25 c (with osc, tbm, current sense) 25 c (with osc, tbm) 25 c ?40 c to 85 c (with osc, tbm, current sense, lvi) ?40 c to 85 c (with osc, tbm, current sense) ?40 c to 85 c (with osc, tbm) ?40 c to 85 c i dd ? ? ? ? ? ? ? ? ? ? ? 24 18 7.5 50 12 9 2 ? ? ? ? 40 30 15 150 40 30 10 180 50 40 15 ma ma ma a a a a a a a a digital i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por re-arm voltage (6) v por 0?100mv por rise-time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v tst 1.4 v dd ?8v
mc68hc08sr12 mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor mc68hc08sr12 399 a.8.2 3.0v dc elect rical characteristics pullup resistors (8) ptd[0:7] configured as kbi[0:7] rst , irq1 , irq2 r pu1 r pu2 24 24 35 35 42 42 k ? k ? low-voltage inhibit, trip falling voltage v lvii5 3.80 4.15 4.45 v low-voltage inhibit, trip rising voltage v lvii5 3.95 4.30 4.60 v schmitt trigger input low level trip voltage rst , irq1 , irq2 , kbi[0:7] v scmtl ?1.21? v schmitt trigger input high level trip voltage rst , irq1 , irq2 , kbi[0:7] v scmth ?1.65? v notes : 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as in puts. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source. all inpu ts 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as in puts. osc2 capacitance linearly affects wait i dd . 5. stop i dd measured with osc1 grounded, no port pins sourcing current. 6. maximum is highest vo ltage that por is guaranteed. 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. 8. r pu1 and r pu2 are measured at v dd = 5.0v table a-3. 3v dc el ectrical characteristics characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?1.0ma) pta[0:7], ptb[4:6], ptc[0:7], ptd[0:7] v oh v dd ?0.4 ??v output low voltage (i load = 0.8ma) pta[0:7], ptb[0:6], ptc[0:7], ptd[0:7] v ol ??0.4v led sink current (v drain = 2.0v) pta[0:5], ptc[3:7] v ol ??5?ma input high voltage pta[0:7], ptb[0:6], pt c[0:7], ptd[0:7], rst , irq1 , irq2 , osc1 v ih 0.7 v dd ? v dd v input low voltage pta[0:7], ptb[0:6], pt c[0:7], ptd[0:7], rst , irq1 , irq2 , osc1 v il v ss ? 0.3 v dd v table a-2. 5v dc el ectrical characteristics characteristic (1) symbol min typ (2) max unit
data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 400 mc68hc08sr12 freescale semiconductor mc68hc08sr12 v dd supply current run (3) , f op = 4.0 mhz with adc on with adc off wait (4) , f op = 4.0 mhz stop (5) 25 c (with osc, tbm, lvi) 25 c (with osc, tbm) 25 c ?40 c to 85 c (with osc, tbm, lvi) ?40 c to 85 c (with osc, tbm) ?40 c to 85 c i dd ? ? ? ? ? ? ? ? ? 7 5 2.5 27 5 1.5 ? ? ? 16 12 6 80 12 5 100 15 5 ma ma ma a a a a a a digital i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por re-arm voltage (6) v por 0?100mv por rise-time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v hi 1.4 v dd ? 2.0 v dd v pullup resistors (8) ptd[0:7] configured as kbi[0:7] rst , irq1 , irq2 r pu1 r pu2 24 24 35 35 42 42 k ? k ? low-voltage inhibit, trip voltage (no hysteresis implemented for 3v lvi) v lv i 3 2.32 2.49 2.68 v schmitt trigger input low level trip voltage rst , irq1 , irq2 , kbi[0:7] v scmtl ?0.8?v schmitt trigger input high level trip voltage rst , irq1 , irq2 , kbi[0:7] v scmth ?1.2?v notes : 1. v dd = 2.7 to 3.3 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as in puts. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source. all inpu ts 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as in puts. osc2 capacitance linearly affects wait i dd . 5. stop i dd measured with osc1 grounded, no port pins sourcing current. 6. maximum is highest vo ltage that por is guaranteed. 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. 8. r pu1 and r pu2 are measured at v dd = 5.0v. table a-3. 3v dc el ectrical characteristics characteristic (1) symbol min typ (2) max unit
mc68hc08sr12 mc68hc908sr12mc68hc08sr12 ? rev. 5.0 data sheet freescale semiconductor mc68hc08sr12 401 a.8.3 memory characteristics a.9 rom order numbers these part numbers are generic number s only. to place an order, rom code must be submitted to the rom processing center (rpc). characteristic symbol min max unit ram data retention voltage v rdr 1.3 ? v notes: since mc68hc08sr12 is a rom device, flash memory electrical characteristics do not apply. table a-4. mc68hc08sr12 order numbers mc order number operating temperature range package mc68hc08sr12cb ?40 to +85 c 42-pin sdip (1) notes : 1. sdip = shrink dual in-line package. mc68hc08sr12cfa ?40 to +85 c 48-pin lqfp (2) 2. lqfp = low quad flat pack.
data sheet mc68hc908sr12m c68hc08sr12 ? rev. 5.0 402 mc68hc08sr12 freescale semiconductor mc68hc08sr12

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